Nany Hasan

Minimum fault coverage in reconfigurable arrays

The authors discuss the case in which the redundant elements are arranged in the form of spare rows and spare columns for a rectangular array. Redundant RAMs are examples of such case. A covering is set of rows and columns that are to be replaced by spare rows and spare columns so that all defective elements are replaced. The authors introduce the notion of a critical set, which is a maximum set of rows and columns that must be included in any minimum covering. They show that for a given pattern of defective elements the corresponding critical set is unique. They also present a polynomial-time algorithm for finding the critical set and demonstrate how the concept of critical sets can be used to solve a number of fault-coverage problems.<<ETX>>

Minimum fault covering in reconfigurable arrays

Abstract One way to increase the yeild in chip production is to place redundant elements on the chips and use these redundant elements to replace the defective elements after the chips are fabricated. It is desirable that as few redundant elements are used for replacement as possible since the cost to reconfigure a chip is proportional to the number of redundant elements used. This paper discusses the case in which the redundant elements are arranged in the form of spare rows and spare columns for a rectangular array. Redundant RAMs are examples of such case. A covering is a set of rows and columns that contain all the defective elements in the array. Replacing the rows and columns in the covering with spare rows and columns will then repair the chip. We introduce the notion of a critical set which is a maximum set of rows and columns that must be included in any minimum covering. We show that for a given pattern of defective elements the corresponding critical set is unique . We also present a polynomial-time algorithm for finding the critical set, and demonstrate how the concept of critical sets can be applied to solve a number of fault covering problems.

Fault covers in reconfigurable PLAs

Three kinds of faults are considered: stuck-at faults, bridging faults, and crosspoint faults. A new way of repairing bridging faults is introduced. It is shown that the problem of finding a minimum cover is NP-complete but that a special case of this problem can be formulated as a 2-SAT problem, which can be solved in polynomial time. The problem of finding a feasible cover for RPLAs (reconfigurable programmable logic arrays) with bridging faults alone is shown to be NP-complete. A necessary and sufficient condition on the number of spares for the existence of a feasible cover and an algorithm for finding a minimum feasible cover are presented.<<ETX>>

Fault covering problems in reconfigurable VLSI systems

1 An Overview.- 1.1 Introduction.- 1.2 The Embedding Approach.- 1.3 The Covering Approach.- 1.3.1 Previous Work.- 1.3.2 Physical Implementation Issues in Reconfigurable Design.- 1.4 Overview of Remaining Chapters.- 2 Fault Covers in Rectangular Arrays.- 2.1 Introduction.- 2.2 Admissible Assignments.- 2.3 The Feasible Minimum Cover Problem.- 2.3.1 Critical Sets.- 2.3.2 An Exhaustive Search Algorithm for the Feasible Minimum Cover Problem.- 2.3.3 Experimental Results.- 2.4 The Feasible Cover Problem.- 2.4.1 Excess-k Critical Sets.- 2.4.2 Experimental Results.- 2.5 Two Reconfiguration Problems.- 2.5.1 Reconfiguration with Shared Spares.- 2.5.2 Reconfiguration of Programmable Logic Arrays.- 2.6 Summary.- 3 Fault Covers in Heterogeneous and General Arrays.- 3.1 Introduction.- 3.2 Fault Covers in Heterogeneous Arrays.- 3.2.1 The Feasible Cover Problem.- 3.2.2 The Feasible Minimum Cover Problem.- 3.2.3 The Minimum Feasible Cover Problem.- 3.2.4 The Feasible Cover Problem with multiple Spare Arrays.- 3.2.5 Applications of the Heterogeneous Array Model.- 3.3 Fault Covers in General Arrays.- 3.3.1 The Feasible Cover Problem.- 3.3.2 The Feasible Minimum Cover Problem.- 3.3.3 The Minimum Feasible Cover Problem.- 3.4 Summary.- 4 General Formulation of Fault Covering Problems.- 4.1 Introduction.- 4.2 A General Formulation.- 4.3 Illustrative Examples.- 4.4 Integer Linear Programming Approach.- 4.4.1 The General Transformation.- 4.4.2 Experimental Results.- 4.5 Complexity Analysis of Subcases.- 4.5.1 The Definition of Subcases and Their Complexities.- 4.5.2 Polynomial Time Algorithms.- 4.5.3 NP-Completeness Results.- 4.6 Summary.

A new formulation of yield enhancement problems for reconfigurable chips

The covering problem assigns redundant elements to replace defective elements so that the chip will function properly. A general model that can be used to represent the relationship between redundant elements and defective elements in a uniform way is presented. This model subsumes many of the models discussed in previous approaches. A complete characterization of the complexity of the covering problems in all the subcases of the model, most of which have not been studied before, is given. It is hoped that the formulation will also lead to new ways of designing reconfigurable chips.<<ETX>>

An Integer Linear Programming Approach to General Fault Covering Problems

The probability of having defective elements in a chip increases as chip density increases. One way to increase the yield in chip production is to use reconfigurable chips in which there are redundant elements that can be used to replace the defective elements. The fault covering problem is to assign redundant elements to replace the defective elements such that the chip will function properly. A general formulation to represent the relationship between redundant elements and defective elements in a uniform way was presented in [HaCL88]. Such a formulation subsumes many of the formulations discussed in previous studies. In this paper, we give a general algorithm for the solution of fault covering problems in the general formulation. We transform these problems into integer linear programming problems. The general integer linear programming problem is a well studied combinatorial optimization problem for which there are known methods of solution. To demonstrate the effectiveness of the integer linear programming approach, we studied three different fault covering problems, namely, the fault covering problems for redundant RAMs, the fault covering problems for arrays of RAMs with shared spares, and the fault covering problems for arrays of processors. Our method achieves very good results. It produces optimal solutions using the minimum number of redundant elements. Also, the computation times of our method for all test examples are very short.

A General Model for Fault Covering Problems in Reconfigurable Arrays

An increase in chip density leads to a reduction in the yield of chip production. [Schu78] showed that in most cases, only a small number of elements in defective chips are actually defective. Thus the idea of repairing a chip after fabrication becomes very appealing. Reconfigurable chips are often used for this purpose. These chips contain redundant elements that can be used to repair the defective elements. There are many different ways to reconfigure a chip using redundant elements. The fault covering problem is to assign redundant elements to replace the defective elements such that the chip will function properly. In this paper we introduce a general model to represent the relationships between redundant elements and defective elements in a uniform way. This model generalizes the models discussed in previous approaches. We also give a complete characterization of the complexity of the fault covering problems for all the subcases of our model, most of which have not been studied before.

Disjoint covers in replicated heterogeneous arrays

Reconfigurable chips are fabricated with redundant elements that can be used to replace the faulty elements. The fault cover problem consists of finding an assignment of redundant elements to the faulty elements such that all of the faults are repaired. In reconfigurable chips that consist of arrays of elements, redundant elements are configured as spare rows and spare columns.This paper considers the problem in which a chip contains several replicates of a heterogeneous array, one or more sets of spare rows, and one or more sets of spare columns. Each set of spare rows is identical to the set of rows in the array, and each set of spare columns is identical to the set of columns in the array. Specifically, an ith spare row can only be used to replace an ith row of an array, and similarly with spare columns. Repairing the chip reduces to finding a cover for the faults in each of the arrays. These covers must be disjoint; that is, a particular spare row or spare column can be used in the cover of at most on...

General Formulation of Fault Covering Problems

The relationship between faulty elements and spare elements varies for different classes of reconfigurable chips. In general, this relationship could be very complicated. For example, several spare elements may be required to replace a single faulty element or a spare element may be used to replace several faulty elements in a covering assignment. We begin with an example of a reconfigurable chip illustrating some of the possible relationships between faulty elements and spare elements.

Fault Covers in Rectangular Arrays

The covering approach is used most frequently in rectangular arrays with spare rows and columns. Several examples of such architectures, including reconfigurable random access memories (RRAMs) and processor arrays, were described in Chapter 1. Recall that such architectures comprise an m × n array with S R spare rows and S C spare columns in which each faulty element is replaced by replacing the entire row in which it resides by a spare column. As we have mentioned in Chapter 1, the problem of finding a covering assignment for a faulty array is NP-complete [46]. Consequently, efforts in this area have been in the design of heuristics and exhaustive search algorithms. Heuristics can generally find solutions in a short amount of time, but may not always find solutions when they exist. In contrast, exhaustive search algorithms can always find solutions when they exist, but may require exponential running time in the worst case. In this chapter we propose new techniques that can significantly reduce the running time of exhaustive search algorithms for many of these problems.