Naoki Fujieda

An XOR-Based Approach to Merging Entries for Instruction Register Files

The instruction register file (IRF) is an attractive approach to reduce power consumption, which is essential to many embedded systems. However, the previously proposed IRF implementation is not efficient in merging similar instructions into a single entry in the IRF. In this paper, we propose an XOR-based merging approach that achieves higher efficiency in grouping instructions with simple hardware. Our evaluation shows that the proposed approach can convert 19.6% more dynamic instructions into references of the IRF than the previous techniques, and that it reduces the number of instruction fetches from the cache by 4.8% on average.

Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM

Oblivious RAM (ORAM) is a technique to hide the access pattern of data to untrusted memory along with their contents. Path ORAM is a recent lightweight ORAM protocol, whose derived access pattern involves some redundancy that can be removed without the loss of security. In this paper, we introduce last path caching, which removes the redundancy of Path ORAM with a simpler protocol than an existing scheme. By combining two caching strategies, our technique showed only 0.2% performance loss from the existing one, while keeping the determinacy of the derived access pattern.

An XOR‐based parameterization for instruction register files

The instruction register file (IRF) shortens and obfuscates instruction sequences by compressing multiple instructions into a packed instruction. The IRF could improve its efficiency by parameterization, but the previously proposed parameterization techniques did not extract the similarity of instructions well. In this paper, we propose an XOR-based parameterization to utilize the limited capacity of the IRF more efficiently. According to our evaluation, with an improved algorithm of instruction selection, our approach makes 20.2% more dynamic instructions IRF-resident than the previous techniques. It also reduces the number of instruction fetches from the cache by 6.3% on average. We also confirmed that the hardware overhead of our parameterization was about a quarter of the previous one.

Design trade-offs in SHA-3 multi-message hashing on FPGAs

Hash functions are widely used to check whether the data are correctly transferred. Keccak is an important hash function that was selected as SHA-3 in 2012. In this paper, we propose and evaluate the optimized FPGA implementations of Keccak for multi-message hashing. Our optimizations include a variety of pipeline organizations, retiming of a part of the calculation, and the use of DSP units. According to the evaluation results, our implementation exhibited 52% higher throughput/area than the previous one on a Xilinx Virtex-5 FPGA. Although the above design adopted advanced DSP units that support bitwise XOR, 20% improvement was achieved even on a Spartan-6 with simpler multiply-adders.

A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs

Metastability of RS latches can be a source of entropy for true random number generators (TRNGs). This study presents a new composition of an RS latch using the latch functionality of storage elements of Xilinx FPGAs. Our TRNG is implemented as a soft macro, or RTL description with directives, which is easily integrated into other logic components. According to our evaluation with an Artix-7 FPGA (XC7A35T), our TRNG with 320 latches (716 LUTs and 974 registers) passed the NIST SP 800-22 test suite without post-processing. Also, our new TRNG presented a 2.3x better areadelay product than the existing design to pass the diehard test.

Evaluation of the hardwired sequence control system generated by high-level synthesis

This study presents the application of the commercial High Level Synthesis (HLS) to a hardwired control application with quantitative comparison to the traditional approach that uses logic synthesis with HDL. Though the derived circuits from HLS are comparable to that of logic synthesis, the design trade-offs in HLS are difficult to control. This study also presents the design and evaluation of the whole system of hardwired control with a Xilinx Zynq-7000 FPGA platform. From our experiments, two performance bottlenecks were identified: the RAM for memory elements that serializes the read/write accesses, and data transfer time via the peripheral bus. According to our results, the sole hardwired control was 10 times faster than the original software, while the overall performance was 4 to 50 times worse than the original software. The use of flipflops and dedicated I/O pins are necessary for high-performance systems.

Design and implementation of instruction indirection for embedded software obfuscation

Tamper-aware use of the Instruction Register File (IRF) is presented.Two heuristic algorithms are presented to find sub-optimal IRF assignments against tampering.For a small IRF, our precision-oriented algorithm obtained the optimal assignments in most cases.Our time-oriented algorithm completed the calculation in 16 milliseconds for a 1024-entry IRF.The additional logic amount for a large IRF is comparable to similar techniques. Instruction Register File (IRF) was originally proposed to reduce the power consumption of a microprocessor by providing the indirect access to frequently executed instructions. The IRF is also an attractive and cost-effective unit to protect embedded software from analysis, plagiarism, and falsification. For this purpose, the correspondences between IRF entries and their original instructions must be concealed. This means the instructions in the IRF should be carefully selected both to have more instructions be executed through the IRF and to flatten the distribution of the indices of the IRF.This paper presents two heuristic algorithms, precision-oriented and time-oriented, to find sub-optimal assignments to the IRF. According to the evaluation results, the precision-oriented algorithm obtained the same as or very close to the optimal assignment of an IRF with 48 or less entries. The time-oriented algorithm found a sub-optimal assignment of a 1024-entry IRF in 16 ms, whose precision was 0.5% inferior to the precision-oriented solution at a maximum. The hardware cost of a 1024-entry IRF on an FPGA was modest: two 18 kib block RAM elements and 0.8% increase of the logic elements.

A Complement to Enhanced Instruction Register File against Embedded Software Falsification

Instruction set randomization (ISR), which modifies or enhances instruction coding of processors, is one of the cost-effective techniques to obfuscate embedded software. Using an Instruction Register File (IRF) for ISR was proposed and explored, while the existing technique lacked a protection against falsification of software. This study presents a complementary table to the IRF named Instruction Rejection Register File (IRRF). It forces the processors to use some of the enhanced instruction codes given by the IRF, which are incomprehensible to attackers, rather than their original codes. According to our evaluation, a 512-entry IRRF covered up to 52.5% of the execution and its cost was additional 1.7% of logic and three RAM elements with 15% performance overhead.