Naoto Watanabe
Toshiba
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Publication
Featured researches published by Naoto Watanabe.
Journal of Orthopaedic Trauma | 1997
Takashi Ohe; Kozo Nakamura; Takashi Matsushita; Masayuki Nishiki; Naoto Watanabe; Kunitoshi Matsumoto
A simulation study of distal interlocking of an intramedullary nail was performed using newly devised, portable stereo fluoroscopy. Two intramedullary nails in which ten holes were drilled perpendicular to the long axis and at various angles to the diameter were inserted into a femoral and a tibial bone model. Ten drill bits were drilled freehand into the holes in the nail with the aid of the stereo fluoroscope. All twenty drill bits were seated in the holes in the first attempt. This instrument provides a three-dimensional view in real time, which enables the surgeon to appreciate the three-dimensional relationship between the drill bit and the hole in the nail in the bone model. Distal interlocking of the intramedullary nail is facilitated with the aid of this stereo fluoroscope.
international solid-state circuits conference | 2016
Kei Shiraishi; Yasuhiro Shinozuka; Tomonori Yamashita; Kazuhide Sugiura; Naoto Watanabe; Ryuta Okamoto; Tatsuji Ashitani; Masanori Furuta; Tetsuro Itakura
This paper presents a 1.2e-, 3D-stacked CMOS image sensor (CIS) for mobile applications. A key motivation for using a stacked configuration is to minimize the chip area. Also, since numerous components must be integrated into the bottom chip, a scaled 65nm CMOS process is adopted for the bottom chip. The developed CIS features 1.2e- temporal noise with extremely high power efficiency by employing a multiple-sampling (MS) technique. A 2nd-order incremental ΔΣ ADC with inverter-based switched-capacitor integrator realizes the MS technique with low power [1]. However, an exponential number of samples are required to reduce the quantization noise, and conversion speed worsens with higher bit resolution. An extended counting ADC, which is a blend of folding integration and cyclic ADC, attains high resolution with reduced conversion time [2-3]. However, an op-amp with high open-loop gain is required for good linearity and column-to-column matching characteristics, which increases power consumption. Also it is not suitable for scaled CMOS technology. An alternative approach is a single-slope (SS) based MS technique [4], in which two SS-ADCs convert the same pixel signal, and the readout signal is averaged in the digital domain, but the noise improvement is limited to -3dB and the power consumption and area occupation are roughly doubled.
Archive | 2000
Naoto Watanabe
Archive | 2002
Naoto Watanabe
Archive | 2000
Naoto Watanabe
Archive | 1999
Takuya Sakaguchi; Akira Tsukamoto; Masayuki Nishiki; Naoto Watanabe
Archive | 1999
Masayuki Nishiki; Takuya Sakaguchi; Akira Tsukamoto; Naoto Watanabe; 卓弥 坂口; 明 塚本; 直人 渡▲辺▼; 雅行 西木
Archive | 2006
Naoto Watanabe
Archive | 2012
Motohiro Morisaki; Naoto Watanabe
Archive | 2010
Takashi Hosoe; Atsushi Takeda; Hiroyasu Kunimi; Naoto Watanabe; Akifumi Matsushita