Narbeh Derhacobian

Power and Energy Perspectives of Nonvolatile Memory Technologies

Discrete and embedded nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 25 years. In recent years, the proliferation of personal media devices such as multimedia-enabled cell phones, personal music players, and digital cameras has accelerated the adoption of silicon-based solid state storage cards in consumer markets. Despite the expanded use of nonvolatile memory technologies in a variety of integrated systems, little has changed with respect to the core technology and cells that hold the data when power has been turned off. Today, floating gate (FG) or oxide-nitride-oxide trapped charge (ONO) cell structures dominate as the core technology behind all NVM devices and embedded blocks. All of the nonvolatile memory devices in production today based on these technologies require high voltage in excess of 5-8 V to operate primarily due to the fundamental nature of core cells and the physics of charge storage mechanisms. These are huge overvoltage requirements considering that the transistors in the logic block require substantially lower voltages (e.g., sub-65 nm logic CMOS operate at less than 1 V). Integrating such high-voltage operation in advanced logic processes such as 65 nm or below logic CMOS process is yet another challenge limiting the exploitation of NVM for low-power embedded applications. The high voltage requirement for operation of these core cells has put strains on the continued scaling of todays discrete and embedded NVM technologies. Furthermore, future ultralow-power and subthreshold CMOS applications such as energy starved electronics require operations at sub-500 mV which clearly set forth significant challenges in integrating todays NVM technologies as nonvolatile storage elements for such systems. Several emerging technologies are competing to become the building blocks of next-generation nonvolatile memory solutions. Each of these emerging technologies has unique characteristics in terms of physical scaling, voltage scaling, cost, performance, and power features which differ from todays FG and ONO based technologies. This paper reviews the fundamental characteristics of current nonvolatile memory technologies as well as several promising emerging technologies from energy and power perspectives and specifically discusses the suitability of each one for use in ultralow-power and subthreshold CMOS applications.

Quantized Conductance in

Ag/GeS2/W conductive-bridge random access memory (CBRAM) cells are shown to program at room temperature to conductance levels near multiples of the fundamental conductance G0 = 2e2/h. This behavior is not accounted for in the traditional view that the conductance of a CBRAM cell is a continuous variable proportional to the maximum current allowed to flow during programming. For on -state resistances on the order of 1/G0 = 12.9 kΩ or less, quantization implies that the Ag “conductive bridge” typically contains a constriction, or even an extended chain, that can be as narrow as a single atom. Implications for device modeling and commercial applications are discussed.