Narendra V. Shenoy

Logic synthesis for programmable gate arrays

The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architectures: table-look-up and multiplexor-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources.

Improved logic synthesis algorithms for table look up architectures

The authors address the problem of synthesis for a popular class of programmable gate array architecture-the table look-up architectures. These use lookup table memories to implement logic functions. The authors present improved techniques for minimizing the number of table look up blocks used to implement a combinational circuit. On average, the results obtained on a set of benchmarks are 15-29% better than results obtained by previous approaches.<<ETX>>

Performance directed synthesis for table look up programmable gate arrays

The authors address the problem of delay optimization for programmable gate arrays. The main considerations are the number of levels in the circuit and the wiring delay. The authors propose a two-phase approach: the first phase involves delay optimizations during logic synthesis before placement, while the second uses logic resynthesis in the case of a timing-driven placement technique. Results and comparisons on benchmarks are presented.<<ETX>>

Minimum padding to satisfy short path constraints

Combinational circuits are often embedded in synchronous designs with memory elements at the input and output ports. A performance metric for a circuit is the cycle time of the clock signal. Correct circuit operation requires that all paths have a delay that lies between an upper bound and a lower bound. Traditional approaches in delay optimization for combinational circuits have dealt with methods to decrease the delay of the longest path. We address the issue of satisfying the lower bound constraints. Such a problem also arises in wave pipelining of circuits. We propose to handle short path constraints as a post processing step after traditional delay optimization techniques. There are two issues presented in this paper. We first discuss necessary and sufficient conditions for successful delay insertion without increasing delays of any long paths. In the second part, we present a naive approach to padding delays (greedy heuristic) and an algorithm based on linear programming. We describe an application of the theory to wave pipelining of circuits. Results are presented on a set of benchmark circuits, using two delay models.

Verifying clock schedules

Timing verification and optimization have been formulated as mathematical programming problems. The computational aspects of using such a formulation for verifying clock schedules are considered. The formulation can have multiple solutions, and these extraneous solutions can cause previously published algorithms to produce incorrect or misleading results. The conditions under which multiple solutions exist are characterized, and it is shown that even when the solution is unique, the running times of these previous algorithms can be unbounded. By contrast, a simple polynomial time algorithm for clock schedule verification is exhibited. The algorithm was implemented and used to check the timing of all the circuits in the ISCAS-89 benchmark suite. Observed running times are linear in circuit size and quite practical. >

Graph algorithms for clock schedule optimization

For performance-driven synthesis of sequential circuits, the optimal clocking problem is considered, and it is shown that it is reducible to a parametric shortest path problem. Constraints are used that take into account both the short and long paths. The main contributions are efficient graph algorithms to solve the set of constraints necessary for correct clocking.<<ETX>>

Retiming of circuits with single phase transparent latches

An algorithm is developed for the retiming of single phase sequential circuits with level sensitive (transparent) latches. A set of constraints that permit retiming and optimal clock cycle computation are also developed. It is shown that a design with edge-triggered latches may be tested for speed-up using transparent latches.<<ETX>>

On the temporal equivalence of sequential circuits

The authors extend the abstract notion of temporal behavior to compare arbitrary circuits with arbitrary multiphase clocking schemes. They consider the input-output behavior of circuits with respect to time. Properties are discussed that remain invariant under certain transformations. Constraints are derived that permit a legal retiming in the case of multiphase sequential circuits with edge triggered and/or transparent latches. For a particular design style an efficient procedure is described to check for temporal equivalence of sequential circuits. A model and a formal definition for the temporal behavior of an arbitrary multiphase circuits and an algorithm for formal verification of the temporal behavior of circuits are outlined.<<ETX>>

Resynthesis of Multi-Phase Pipelines

This paper describes an algorithm for deriving necessary and sufficient constraints for a multi-phase sequential pipeline to operate at a target clock cycle. Constraints on delays of the pipeline stages are used to drive a combinational logic delay optimizer to resynthesize the pipeline stages for improved performance. A main advantage of such an approach is that a global picture of the distribution of delays in the circuit is obtained. It also permits safe cycle stealing through level-sensitive latches across pipeline stages.

Linear programming for hazard elimination in asynchronous circuits

Hazards can be globally eliminated from an asynchronous circuit synthesized from a Signal Transition Graph by repeatedly solving an appropriate Linear Program. This article describes how to analyze the STG specification and the synthesized circuit, using bounded delay information, to formulate the problem and use a branch-and-bound procedure to solve it. Known information about the environment delays can be expressed as time bounds on the external signal transitions, and it can be exploited by the proposed methodology.