Nasser Alaraje

Evaluating the performance of IEEE 802.11 network using RTS/CTS mechanism

In order to effectively analyze the performance of wireless local area networks (WLANs), it is important to identify what types of network settings can cause bad performance. Low throughput, high packet loss rate, delayed round trip time (RTT) for packets, increased retransmissions, and increased collisions are the main attributes to look for when analyzing poor network performance. We use the OPNET Modeler [1] to simulate the RTS/CTS mechanism to evaluate the performance of IEEE 802.11 MAC protocol [6]. We have simulated two scenarios with and without RTS/CTS mechanism enabled on network nodes. We have concluded our findings by comparing the total WLAN retransmissions, data traffic sent/received, WLAN Delay of two scenarios. RTS/CTS mechanism is helpful to reduce the number of retransmissions if hidden node problem persists in network scenarios.

SoFPGA (Sysytem-on-FPGA) architecture: Performance analysis

New system-on-chip (SoC) design techniques are necessary to address the communication requirements for future SoC. The currently used bus-centered approach becomes an inappropriate choice because of its limitation as a shared medium that restricts the scalability of the communication architecture. Also, long bus wires result in performance degradation due to the increased capacitive load. The long wires also consume more power to drive all of intellectual property cores, IP Cores, on the bus. New communication architecture, the NoFPGA (network-on-FPGA), for future SoFPGA (System-on-FPGA) has been presented. The paper details the architecture of a NoFPGA router. The interconnecting issues in SoC design methodology built in a single FPGA device are addressed. Mainly, the problem of achieving efficient NoFPGA performance through investigating the best topology is addressed. Results of the work show that the 2D Torus NoFPGA outperforms the 2D Mesh NoFPGA.

Performance analysis of future System-on-FPGA topology candidates

New System-on-Chip (SoC) design techniques are necessary to address the communication requirements for future SoC. The currently used Bus-Centered approach becomes an inappropriate choice because of its limitation as a shared medium that restricts the scalability of the communication architecture. Also, long bus wires result in performance degradation due to the increased capacitive load. The long wires also consume more power to drive all of Intellectual Property Cores, IP Cores, on the bus. New communication architecture, the NoFPGA (Network-on-FPGA), for future SoFPGA (System-on-FPGA) has been presented. The paper details the architecture of a NoFPGA router. The interconnecting issues in SoC design methodology built in a single FPGA device are addressed. Mainly, the problem of achieving efficient NoFPGA performance through investigating the best topology is addressed. Results of the work show that the 2D Torus NoFPGA outperforms the 2D Mesh NoFPGA. On the other hand, Power estimate analysis showed that the Mesh NoFPGA represents a 30% power drop compared to the equivalent Torus NoFPGA which makes the Mesh NoFPGA is a better candidate for power critical application.

Technology driven university and community college collaboration: Faculty training on ARM microcontrollers

The electronics world is undergoing a transformation in the underlying technologies used to create new products for the worlds consumers. The movement to reconfigurable electronics using microcontrollers is sweeping the electronics world in the rush to create smaller, faster, and more flexible consumer and industrial devices. Microcontrollers are becoming one of the most exciting devices in history. At the core content of microcontroller technology is ARM microcontroller, the ARM processor is an industry standard with annual sales of 5 billion units, and it will increase as the demand for powerful, low-power electronics increases. An engineers and technicians exposure to this technology is critical in order to remain competitive. To meet this industrial needs, university programs are updating curricula with courses in ARM microcontroller technology. Partners on this project have years of successful National Science Foundation (NSF) projects, educating and training hundreds of instructors and introducing thousands of students to advanced technologies. This paper will discuss the offering of a Professional Development workshop on ARM microcontrollers for electrical engineering technology faculty as part of an NSF grant. The project goals are to provide colleges with up-to-date educational equipment, educational resources and promote best practices to enable instructors to teach advanced technologies.

Design of a pneumatically powered wearable exoskeleton with biomimetic support and actuation

Powered exoskeletons are designed to assist and protect the wearer. Depending on the situation they may be used to protect soldiers and construction workers, aid the survival of people in dangerous environments, or assist patients in rehabilitation. Regardless of the application there are strict requirements for designing and producing exoskeleton suites. They must be durable but light weight and flexible, have reliable power control and modulation, capable of detecting unsafe and invalid motions, and may require significant weight lifting capabilities. In this article we present an on-going research on robotic exoskeleton replicating of human muscle functions. A single wearable knee-joint prototype described in this article combines the use of soft pneumatic muscle-like actuators and a control system based off the users own natural muscle signals. The Pneumatic Exoskeleton uses bioelectrical signals to detect movement intention from the pilot. This paper details the technical design aspects of a lower-limb robotic exoskeleton with possibility of further expansion to fully functioning robotic exoskeleton suit.

Impact of Buffering Mechanism on Sofpga IP Router Cost

In todays world of advanced technology numerous applications are computational intensive. This created an opportunity for the development of new System-on-Chip (SoC) design techniques to allow easy IP cores (Intellectual Property cores) re-use and integration under time-to-market pressure. New System-on-Chip (SoC) design techniques are necessary to address the communication requirements for future SoC. New communication architecture, the NoFPGA, for future SoFPGA has been presented. The IP router is the heart of NoFPGA. The design cost of IPRouter Buffering, the most expensive building block, is evaluated based on two different implementation approaches. First, IPRouter buffering based on distributed memory. Second, IPRouter buffering based on Embedded Block RAMs.