Natarajan Viswanathan

FastPlace: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model

In this paper, we present FastPlace-a fast, iterative, flat placement algorithm for large-scale standard cell designs. FastPlace is based on the quadratic placement approach. The quadratic approach formulates the wirelength minimization problem as a convex quadratic program that can be solved efficiently by some analytical techniques. However it suffers from some drawbacks. First, the resulting placement has a lot of overlap among cells. Second, the resulting total wirelength may be long as the quadratic wirelength objective is only an indirect measure of the linear wirelength. Third, existing net models tend to create a lot of nonzero entries in the connectivity matrix that slows down the quadratic program solver. To handle the above problems we propose: 1) an efficient cell shifting technique to remove cell overlap from the quadratic program solution and also accelerate the convergence of the solver. This technique produces a global placement with even cell distribution in a very short time; 2) an iterative local refinement technique to reduce the wirelength according to the half-perimeter measure; and 3) a hybrid net model that is a combination of the traditional clique and star models. This net model greatly reduces the number of nonzero entries in the connectivity matrix and results in a significant speedup of the solver. Experimental results show that FastPlace is on average 13.4/spl times/,102/spl times/, and 19.9/spl times/ faster than state-of-the art academic placers Capo, Dragon, and Gordian-Domino, respectively, on a set of IBM benchmarks.

FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control

In this paper, we present FastPlace 3.0 - an efficient and scalable multilevel quadratic placement algorithm for large-scale mixed-size designs. The main contributions of our work are: (1) A multilevel global placement framework, by incorporating a two-level clustering scheme within the flat analytical placer FastPlace (Viswanathan and Chu, 2005) and Viswanathan et al., 2006), (2) An efficient and improved iterative local refinement technique that can handle placement blockages and placement congestion constraints. (3) A congestion aware standard-cell legalization technique in the presence of blockages. On the ISPD-2005 placement benchmarks (Nam et al., 2005), our algorithm is 5.12times, 11.52times and 16.92times faster than mPL6, Capo10.2 and APlace2.0 respectively. In terms of wirelength, we are on average, 2% higher as compared to mPL6 and 9% and 3% better as compared to Capo10.2 and APlace2.0 respectively. We also achieve competitive results compared to a number of academic placers on the placement congestion constrained ISPD-2006 placement benchmarks (Nam, 2006).

An efficient and effective detailed placement algorithm

In the past few years, there has been a lot of research in the area of global placement. In comparison, not much attention has been paid to the detailed placement problem. Existing detailed placers either fail to improve upon the excellent solution quality enabled by good global placers or are very slow. To handle the above problems, we focus on the detailed placement problem. We present an efficient and effective detailed placement algorithm to handle the wirelength minimization problem. The main contributions of our work are: (1) an efficient Global Swap technique to identify a pair of cells that can be swapped to reduce wirelength; (2) a flow that combines the Global Swap technique with other heuristics to produce very good wirelength; (3) an efficient single-segment clustering technique to optimally shift cells within a segment to minimize wirelength. On legalized mPL5 global placements on the IBM standard-cell benchmarks, our detailed placer can achieve 19.0%, 13.2% and 0.5% more wirelength reduction compared to Fengshui5.0, rowironing and Domino respectively. Correspondingly we are 3.6/spl times/ 2.8/spl times/ and 15/spl times/ faster. On the ISPD05 benchmarks (Gi-Joon Nam et al., 2005), we achieve 8.1% and 9.1% more wirelength reduction compared to Fengshui5.0 and rowironing respectively. Correspondingly we are 3.1/spl times/ and 2.3/spl times/ faster.

FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model

In this paper, we present FastPlace-a fast, iterative, flat placement algorithm for large-scale standard cell designs. FastPlace is based on the quadratic placement approach. The quadratic approach formulates the wirelength minimization problem as a convex quadratic program that can be solved efficiently by some analytical techniques. However it suffers from some drawbacks. First, the resulting placement has a lot of overlap among cells. Second, the resulting total wirelength may be long as the quadratic wirelength objective is only an indirect measure of the linear wirelength. Third, existing net models tend to create a lot of nonzero entries in the connectivity matrix that slows down the quadratic program solver. To handle the above problems we propose: 1) an efficient cell shifting technique to remove cell overlap from the quadratic program solution and also accelerate the convergence of the solver. This technique produces a global placement with even cell distribution in a very short time; 2) an iterative local refinement technique to reduce the wirelength according to the half-perimeter measure; and 3) a hybrid net model that is a combination of the traditional clique and star models. This net model greatly reduces the number of nonzero entries in the connectivity matrix and results in a significant speedup of the solver. Experimental results show that FastPlace is on average 13.4/spl times/,102/spl times/, and 19.9/spl times/ faster than state-of-the art academic placers Capo, Dragon, and Gordian-Domino, respectively, on a set of IBM benchmarks.

RQL: global placement via relaxed quadratic spreading and linearization

This paper describes a simple and effective quadratic placement algorithm called RQL. We show that a good quadratic placement, followed by local wirelength-driven spreading can produce excellent results on large-scale industrial ASIC designs. As opposed to the current top performing academic placers [4,7,11], RQL does not embed a linearization technique within the solver. Instead, it only requires a simpler, pure quadratic objective function in the spirit of [8,10,23]. Experimental results show that RQL outperforms all available academic placers on the ISPD-2005 placement contest benchmarks. In particular, RQL obtains an average wire- length improvement of 2.8%, 3.2%, 5.4%, 8.5%, and 14.6% versus mPL6 [5], NTUPlaceS [7], Kraflwerk [20], APlace2.0 [11], and Capo10.2 [18], respectively. In addition, RQL is three, seven, and ten times faster than mpL6, Capo10.2, and APlace2.0, respectively. On the ISPD-2006 placement contest benchmarks, on average, RQL obtains the best scaled wirelength among all available academic placers.

Handling complexities in modern large-scale mixed-size placement

In this paper, we propose an effective algorithm flow to handle large-scale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the global level. The flow consists of four steps: (1) The objects in the original netlist are clustered into blocks; (2) Floorplanning is performed on the blocks; (3) The blocks are shifted within the chip region to further optimize the wirelength; (4) With big macro locations fixed, incremental placement is applied to place the remaining objects. There are several advantages of handling placement at the global level with a floorplanning technique. First, the problem size can be significantly reduced. Second, exact HPWL can be minimized. Third, precise object distribution can be achieved so that legalization only needs to handle minor overlaps among small objects in a block. Fourth, rotation and various placement constraints on macros can be handled. To demonstrate the effectiveness of this new flow, we implement a high-quality floorplan-guided placer called FLOP. We also construct the Modern Mixed-Size (MMS) placement benchmarks which can effectively represent the complexities of modern mixed-size designs and the challenges faced by modern mixed-size placers. Compared with state-of-the-art mixed-size placers and leading macro placers, experimental results show that FLOP achieves the best wirelength, and easily obtains legal solutions on all circuits.

FastPlace 2.0: an efficient analytical placer for mixed-mode designs

In this paper, we present FastPlace 2.0 - an extension to the efficient analytical standard-cell placer - FastPlace, to address the mixed-mode placement problem. The main contributions of our work are: (1) Extensions to the global placement framework of FastPlace to handle mixed-mode designs. (2) An efficient and optimal minimum perturbation macro legalization algorithm that is applied after global placement to resolve overlaps among the macros. (3) An efficient legalization scheme to legalize the standard cells among the placeable segments created after fixing the movable macros. On the ISPD 02 mixed-size placement benchmarks, our algorithm is 16.8times and 7.8times faster than state-of-the-art academic placers Capo 9.1 and Feng-shui 5.0 respectively. Correspondingly, we are on average, 12% and 3% better in terms of wirelength over the respective placers

FastPlace: an analytical placer for mixed-mode designs

Modern designs often contain a combination of a large number of standard cells and macro blocks. Traditionally large macro blocks are handled at the floorplanning level, after which their positions are fixed. The standard cells are then handled during the placement level. Current designs can have hundreds of large and medium sized macro blocks and a large number of standard cells. As a result, traditional floorplanning techniques cannot scale to this problem, both in terms of runtime and solution quality. Hence a technique is required to simultaneously handle this combination of placeable objects.In this paper, we present a combined placement and floorplanning approach for mixed-mode placement. We extend the efficient analytical placement algorithm FastPlace by integrating a simulated annealing based floorplanner to solve the global placement problem for mixed-mode designs. We also present an efficient and effective detailed placement algorithm to improve the wirelength of the global placement solution based on a greedy swapping heuristic.