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Nathan C. Buck

IBM

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Featured researches published by Nathan C. Buck.

custom integrated circuits conference | 1996

Gate-array library design using local interconnect

Larry Wissel; Douglas W. Stout; Nathan C. Buck

An ASIC gate-array library has been created in 0.4 /spl mu/m CMOS technology using a local interconnect level. The gate-array cells in this library are denser than their counterparts in a library without local interconnect. The comparison of two benchmarks, including a 520K-gate ASIC routed with both libraries, further shows that the local interconnect allows higher density of ASIC designs due to more efficient use of the global inter-connect layers.

Archive | 2008

METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS

Nathan C. Buck; John P. Dubuque; Eric A. Foreman; Peter A. Habitz; Kerim Kalafala; Peihua Qi; Chandramouli Visweswariah; Xiaoyue Wang

Archive | 2007

Estimation of process variation impact of slack in multi-corner path-based static timing analysis

Nathan C. Buck; John P. Dubuque; Eric A. Foreman; Peter A. Habitz; Kerim Kalafala; Jeffrey Mark Ritzinger; Xiaoyue Wang

Archive | 2009

TIMING CLOSURE ON MULTIPLE SELECTIVE CORNERS IN A SINGLE STATISTICAL TIMING RUN

Nathan C. Buck; Brian M. Dreibelbis; John P. Dubuque; Eric A. Foreman; Peter A. Habitz; Jeffrey G. Hemmett; Susan K. Lichtensteiger; Natesan Venkateswaran; Chandramouli Visweswariah; Xiaoyue Wang

Archive | 2009

Chip design and fabrication method optimized for profit

Nathan C. Buck; Howard H. Chen; James P. Eckhardt; Eric A. Foreman; James C. Gregerson; Peter A. Habitz; Susan K. Lichtensteiger; Chandramouli Visweswariah; Tad J. Wilder

Archive | 2008

METHODS FOR IDENTIFYING FAILING TIMING REQUIREMENTS IN A DIGITAL DESIGN

Nathan C. Buck; John P. Dubuque; Eric A. Foreman; Peter A. Habitz; Chandramouli Visweswariah

Archive | 2007

Variable Threshold System and Method For Multi-Corner Static Timing Analysis

Nathan C. Buck; John P. Dubuque; Eric A. Foreman; Peter A. Habitz; Kerim Kalafala; Peihua Qi; Chandramouli Visweswariah; Xiaoyue Wang

Archive | 2008

Methods for practical worst test definition and debug during block based statistical static timing analysis

Nathan C. Buck; Eric A. Foreman; James C. Gregerson; Jeffrey G. Hemmett

Archive | 2011

METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR PERFORMING A PARAMETERIZED STATISTICAL STATIC TIMING ANALYSIS (SSTA) OF AN INTEGRATED CIRCUIT TAKING INTO ACCOUNT SETUP AND HOLD MARGIN INTERDEPENDENCE

Nathan C. Buck; Brian M. Dreibelbis; John P. Dubuque; Eric A. Foreman; Peter A. Habitz; Jeffrey G. Hemmett; Natesan Venkateswaran; Chandramouli Visweswariah; Xiaoyue Wang; Vladimir Zolotov

Archive | 2008

METHOD TO IDENTIFY TIMING VIOLATIONS OUTSIDE OF MANUFACTURING SPECIFICATION LIMITS

Nathan C. Buck; John P. Dubuque; Eric A. Foreman; Peter A. Habitz; Chandramouli Visweswariah

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Eric A. Foreman

IBM

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Chandramouli Visweswariah

IBM

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Peter A. Habitz

IBM

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John P. Dubuque

IBM

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Jeffrey G. Hemmett

IBM

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Natesan Venkateswaran

IBM

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Brian M. Dreibelbis

IBM

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Kerim Kalafala

IBM

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Vladimir Zolotov

IBM

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Xiaoyue Wang

IBM

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