Nathaniel Rollins

A Comparison of fault-tolerant memories in SRAM-based FPGAs

This paper compares the effectiveness and cost of different fault-tolerant techniques for FPGA memories (BRAMs, LUTRAMs, and SRLs). TMR, parity with duplication, compliment duplicate (CD) with duplication, single-error correction/double-error detection (SEC/DED), and SEC/DED with duplication are the techniques used in this study to protect FPGA memories. Memory scrubbing is also added to each of these techniques. The effectiveness of each technique is measured by the number of sensitive bits in each design as well as the number of critical failures. A critical failure is defined as an upset whose effects can only be repaired through device reconfiguration. Cost is measured in terms of FPGA slices and BRAMs. This study finds that for BRAMs and LUTRAMs scrubbing with TMR provides the best protection. For SRLs scrubbing is unnecessary, and TMR provides the best protection. This study also provides a variety of reliability-area trade-off points with fault-tolerant techniques other than TMR.

Dynamic reconfiguration for management of radiation-induced faults in FPGAs

Summary form only given. We describe novel methods of exploiting the partial, dynamic reconfiguration capabilities of Xilinx Virtex 1000 FPGAs to manage transient faults due to radiation in space environments. The on-orbit fault detection scheme uses a radiation-hardened reconfiguration controller to continuously monitor the configuration bit streams of 9 Virtex FPGAs and to correct errors by partial, dynamic reconfiguration of the FPGAs while they continue to execute. To study single event upset (SEU) impact on our signal processing applications, we use a novel fault injection technique to corrupt configuration bits, thereby simulating SEU faults. By using dynamic reconfiguration, we can run the corrupted designs directly on the FPGA hardware, giving many orders of magnitude speed-up over purely software techniques. The fault injection method has been validated against proton beam testing, showing 97.6% agreement. Our work highlights the benefits of dynamic reconfiguration for space-based reconfigurable computing.

A multi-layered XML schema and design tool for reusing and integrating FPGA IP

Reconfigurable computing systems remain difficult to use and program. One way to increase design productivity for these systems is through reuse of previously developed and verified intellectual property (IP) cores. This paper presents CHREC XML, a XML schema that facilitates IP reuse by encapsulating the details of reusable IP cores at multiple levels of abstraction. This schema is independent from any design language or tool and can be used by any tool to understand many details about the interface of a reusable circuit. An IP integration tool was also created based on this schema to demonstrate the ease of IP reuse when cores are described in this meta-data description. This IP integration tool allows a designer to easily select and integrate IP cores from a variety of languages/tools and automatically run the appropriate tools to generate the cores in a form usable by downstream implementation tools.

Reliability of a softcore processor in a commercial SRAM-based FPGA

Softcore processors are an attractive alternative to using radiation-hardened processors in space-based applications. Unlike traditional processors however, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). This paper applies two common SEU mitigation techniques, TMR with checkpointing and DWC with checkpointing, to the LEON3 softcore processor. The improvement in reliabilty over an unmitigated version of the processor is measured using three metrics: the architectural vulnerability factor (AVF), mean time to failure (MTTF), and mean useful instructions to failure (MuITF). Using configuration memory fault injection, we found that DWC with checkpointing improves the MTTF and MuITF by over 35x, and that TMR with triplicated input and outputs improves the MTTF and MITF by over 6000x.

An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing

The reuse of intellectual property (IP) cores within reconfigurable computing systems is a promising approach for improving the productivity of reconfigurable system design. Further, there are a large variety of reusable IP cores available for a variety of application-specific functions. These cores, however, are created from different design tools and are difficult to integrate into a single reconfigurable system design. To facilitate the reuse of these cores, an XML schema has been created for representing the essential details of a core in a reconfigurable computing design environment. This paper presents this XML schema and describes how it can be used to facilitate reuse in reconfigurable computing systems.