Nattha Jindapetch

A study of the edge detection for road lane

This article presents an investigation of an optimum algorithm for edge detection in order to use in the road lane detection process. The main issues, including the speed, the accuracy, and the limited resources, were taken to consider for the realization on the FPGA technology. The edge detection algorithms of Canny, Prewitt, Sobel and Roberts were compared using MATLAB. A number of road images were captured by a video camera with the image size of 640x480 pixels and the frame rate of 30 fps. In addition, a mask filter was applied to remove red, green, and blue values to help the edge detection process be more efficient. From the experimental results, the Canny algorithm was the most time consuming process, and gave too many lines outside the road lane. Among these, the Roberts algorithm is not only the smallest size, but also gained the fastest speed (3.14 times faster than the Canny algorithm) and the most accurate one to detect the lines of the actual road lanes.

Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times

This paper proposes new scheduling methods for asynchronous circuits with bundled-data implementations. Since operations in asynchronous circuits start after the completion of a previous operation, this method approximates the set of start times for each operation using the delay of the resources. Next, this method decides on control steps from the approximated sets of start times, which are used in scheduling algorithms. This paper extends two scheduling algorithms used for synchronous circuits so that the approximated sets of start times and the decided control steps are used. Finally, this paper shows the effectiveness of our proposed methods by comparing scheduling results with ones obtained by the original two scheduling algorithms.

Wireless ESD Event Locator Systems in Hard Disk Drive Manufacturing Environments

This paper presents two wireless systems, namely, an electromagnetic interference (EMI)-strength-based system and a received signal strength indicator (RSSI)-based system, that locate electrostatic discharge (ESD) events in hard disk drive (HDD) manufacturing environments. The EMI-strength-based system is composed of four EMI detectors and estimates an ESD event position using an enhanced trilateration method. The RSSI-based system consists of three stationary wireless sensor nodes and one mobile wireless sensor node. The stationary nodes provide reference positions, whereas the mobile node is equipped with an EMI detector, which is used to detect an ESD event throughout the manufacturing line. Subsequently, the ESD event position is estimated by an RSSI-based localization method. In this RSSI-based system, a new method is also introduced to compensate the attenuated RSSI values by using a neural network and various transmission powers. Both systems were evaluated in a real HDD setting, and their advantages and disadvantages are discussed here. The evaluation results indicate that both systems worked well. However, the RSSI-based system can support a larger area compared with the EMI-strength-based system.

ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation

In this paper, we propose a new scheduling method for asynchronous circuits in bundled-data implementation. The method is based on integer linear programming (ILP) which explores an optimum schedule under resource or time constraints. To schedule descriptions with many operations, our method approximate start times of operations and formulate an ILP based on the approximated start times. Because less numbers of variables and constraints are required compared to the traditional ILP formulation, the schedule of operations is determined in short time preserving the quality of resulting circuit.

Scheduling & resources sharing technique for adaptive LMS filter

This paper presents a scheduling & resources sharing technique for adaptive LMS (Least-Mean-Square) filter with low power consumption and low resources utilization. It used an 8-bit fixed-point arithmetic representation for the adaptive filter system based on FPGA. The design has been synthesized and simulated in Xilinx ISE. LMS algorithm is widely used in the adaptive filter for noise cancellation system or hearing aid system. We verified the parameter step size u, through simulated the LMS algorithm on MATLAB. And then, we implemented and simulated the original LMS circuit and the proposed LMS circuit which use the scheduling & resources sharing technique design in Xilinx ISE. We found that the proposed circuit uses resources less than the original circuit. Based on the XPower Analyzer tool, the power consumption is estimated. The results showed that the proposed circuit dissipates less power than the original circuit. It nearly economizes 36.4% power consumption compared with the original one.

A Novel FPGA-Based Multi-Channel Multi-Interface Wireless Node: Implementation and Preliminary Test

The implementation and the preliminary test of a novel FPGA-based Multi-Channel Multi-Interface (MCMI) wireless node is presented in this paper. The MCMI wireless node was developed using a Xilinx Spartan-3E XC3S500E FPGA development board. The CC2500 RF transceivers as low-cost low-power wireless radio modules operating in 2.4 GHz ISM band were connected with the FPGA board via a Serial Peripheral Interface (SPI). The implementation result shows that the designed FPGA-based MCMI wireless node architecture uses small amount of resources of the Xilinx Spartan-3E XC3S500E FPGA. Consequently, we can further include more algorithms or functions on the top of our proposed system. The experimental result from a preliminary test scenario also demonstrates that the FPGA-based MCMI wireless node improves the packet delivery ratio to reach 100 % while varying traffic loads.

SDSoC based development of vehicle counting system using adaptive background method

This paper presents a processing system of vehicle detection and counting for a camera on the city street using a heterogeneous ARM/FPGA processor and Xilinx SDSoC (Software-Defined System on Chip). An adaptive background method for reducing the impact of environment have been developed by analyzing luminance approximation changes over time and luminance approximation changes suddenly to improve background image of the object and to eliminate shadows so that the process of vehicles detecting and counting worked effectively.

Document Withdrawn From IEEE Xplore Self-Sensing Actuation Circuit for PZT Micro-actuator in HDDs

This paper presents a new self-sensing actuation (SSA) circuit for using the piezoelectric (PZT) micro-actuator as both an actuator and a sensor simultaneously. The proposed SSA circuit senses the voltage signal generated by the PZT micro-actuator at operating frequencies, while the control voltage applied to the same PZT micro-actuator is not affected. The components of the proposed SSA circuit are minimized to allow easy balancing and implementation. In simulations, the proposed SSA circuit had similar characteristics to the conventional SSA circuit. In experiments, the proposed SSA circuit was tested with a commercial hard disk drive (HDD). The results show that the proposed SSA circuit does not affect the conventional read/write (R/W) head positioning control system. The frequency response of the PZT micro-actuator measured by the proposed SSA circuit had similar to the frequency response of the R/W head displacement at both the resonant frequency and the operating frequencies. The proposed SSA circuit was also tested at various operating temperatures of the HDD. Errors in the sensing voltage signal caused by the unbalanced SSA circuit clearly correlated to the temperatures from 10 °C to 60 °C.

FPGA-based hardware-in-the-loop verification of dual-stage HDD head position control

This paper presents a design and verification of a digital controller for dual-stage hard disk drive (HDD) head positioning. A continuous time model of an adaptive PID controller of the dual-stage track following control is converted to a stable discrete time model. Then, the optimizations of sampling rate, arithmetic operation bit-width, and control parameters are performed during digital controller design. Xilinx System Generator is used to generate the hardware description language that can be implemented in a real FPGA. Finally, hardware-in-the-loop verification is performed through a hardware board to guarantee the control model. This method can not only accelerate the design cycle of new HDD models, but also achieve high sampling rate precise head position control implementations. From the verification results, our proposed controller can work at 5.64 MHz sampling rate on a low cost FPGA (Xilinx Spartan-III XC3S400) and the position error (3-sigma) is only 4.2138 % of track.