Nauman H. Khan

Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies

3-D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, renders the design of 3-D power delivery a challenge. We investigate in this paper various methods to improve 3-D power delivery. We analyze the impact of through-silicon via (TSV) size and spacing, of controlled collapse chip connection (C4) spacing, and of dedicated power delivery TSVs. In addition to considering typical cylindrical or square metal-filled TSVs (core TSVs), we also investigate using coaxial TSVs for power delivery resulting in reduced routing blockages and added coupling capacitance. Our 3-D evaluation system is composed of a quad-core chip multiprocessor, a memory die, and an accelerator engine, and it is evaluated using representative SPEC benchmark traces. This is the first detailed architectural-level analysis for 3-D power delivery. Our findings provide clear guidelines for 3-D power delivery design. More importantly, we show that it is possible to achieve 2-D-like, or even better, power quality by increasing C4 granularity and by selecting suitable TSV size and spacing.

Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs

Through-Silicon Via (TSV) is a critical interconnect element in 3D integration technology. TSVs introduce many new design challenges. In addition to competing with devices for real estate, TSVs can act as a major noise source throughout the substrate. We present in this paper a comprehensive study of TSV-induced noise as a function of several critical design and process parameters including substrate type, signal slew rate, TSV height, ILD thickness, and TSV-to-device and TSV-to-TSV spacing. We create a SPICE model for simulating TSV-to-device and TSV-to-TSV noise couplings in two different types of substrates: a lightly doped bulk substrate, and a lightly doped thin epitaxial layer on top of a heavily doped bulk. Our SPICE model provides small error when compared with a detailed Finite Element Analysis Method. Our findings show the importance of using a grounded backplane in reducing noise and how coaxial TSVs further mitigate TSV-induced noise.

System-level comparison of power delivery design for 2D and 3D ICs

Three-dimensional integrated circuits (IC) promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, render 3D power delivery design a challenge. In this paper, we provide a system-level comparison of power delivery for 2D and 3D ICs. We investigate various techniques that can impact the quality of power delivery in 3D ICs. These include through-silicon via (TSV) size and spacing, controlled collapse chip connection (C4) spacing, and a combination of dedicated and shared power delivery. Our evaluation system is composed of quad-core chip multiprocessor, memory, and accelerator engine. Each of these modules is running representative SPEC benchmark traces. Our findings are practical and provide clear guidelines for 3D power delivery optimization. More importantly, we show that it is possible to achieve 2D-like or even better power quality by increasing C4 granularity and selecting suitable TSV size and spacing.

Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs

Through-silicon vias (TSVs) in 3-D ICs are a major source of substrate noise, causing performance degradation of neighboring active devices. To reduce this noise, we propose using a tungsten-filled ground plug, a TSV-like structure that connects to ground (GND) and that partially or completely extends through the substrate. We evaluate the impact of plug size and placement on noise isolation. We compare the GND plug technique with two other noise mitigation techniques: using a thicker dielectric liner and using a backside ground plane. Our study demonstrates that the GND plug is a superior technology, effective in mitigating TSV-induced substrate noise by an order of magnitude when compared to the other two techniques. The GND plug offers a more practical noise isolation approach than using a backside ground plane. When compared with increased dielectric thickness, the GND plug offers a 33% reduction in foot print and permits a significantly reduced keep out zone.

GND Plugs: A Superior Technology to Mitigate TSV-Induced Substrate Noise

Through-silicon vias (TSVs) contribute to substrate noise in 3-D ICs, causing performance degradation of neighboring active devices and requiring keep-out zones. To mitigate TSV-induced substrate noise, we propose a new device, the ground (GND) plug, a TSV-like structure that connects to the ground and extends partially or completely through the substrate. We propose two types of GND plugs: a “front-side” plug, connecting to local interconnect of the same die, and a “back-side” plug, connecting to the GND from the substrate side of the die. We perform comprehensive analyses to evaluate the performance of GND plugs for two substrate types, a high-R bulk and a bulk with epitaxial layer. We compare the GND plug technique with existing noise mitigation techniques: a thicker dielectric liner, a guard ring, and a back-side ground plane. When compared with increased dielectric thickness, the front-side GND plug offers a relative 33% area reduction and allows a significantly reduced keep-out zone. The GND plug offers a more practical noise isolation approach than using a back-side ground plane. Our study demonstrates that the GND plug is a superior technology, effective in mitigating TSV-induced substrate noise by an order of magnitude when compared to the other techniques. The back-side GND plug does not compete with active devices for silicon area yet reduces substrate noise significantly.

Early estimation of TSV area for power delivery in 3-D integrated circuits

To harness the full potential of 3-D integrated circuits, analysis tools for early design space exploration are needed. Such tools, targeting multiple design facets and cost trade-off analysis, would allow designers to arrive at major decisions regarding architecture and implementations fabrics. We focus in this paper on the efficient estimation of on-chip power delivery requirements consistent with supply noise limits. We propose a number of algorithms to find the minimum number of through-silicon vias (TSVs) that deliver power with acceptable IR drops. Minimizing the number of TSVs reduces the total silicon die area which is the main recurring cost during fabrication. To compute the TSV requirements realistically, we utilize power traces derived from benchmark-based functional behavior of processors. To speed-up our simulations, we develop a trace selection technique that utilizes the relevant portion of power traces representing the worst load for IR drops. The trace selection scheme reduces the number of simulations by 51×. Using these traces we find the best spatial allocation of TSVs for a 3-D implementation of a processor. The iterative algorithm can be run in approximately one hour on a 40-processor cluster.

Designing TSVs for 3D Integrated Circuits

This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits. It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks. Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a oorplan are available. Finally, the authors explore the use of Carbon Nanotubes for power grid design as a futuristic alternative to Copper.

Virtual Worlds for Young People in a Program Context: Lessons from Four Case Studies

This chapter introduces some of the challenges and opportunities involved in designing, implementing, and evaluating psychoeducational intervention programs that use virtual worlds specifically designed for children. The research is based on over a decade of conducting several studies with different kinds of young people and contexts. The chapter will first present the technology, the Zora three-dimensional (3D) multiuser virtual environment, and the theoretical framework upon which it was designed. Latter it discussed four different case studies in which Zora was used: with a diverse group of children in a multicultural summer camp, with incoming freshman at a northeastern university, with transplant patients at Children’s Hospital Boston, and with children in a network of after school programs all around the world. By presenting each of these case studies, the chapter will focus on eight considerations to take into account when designing and implementing programs that use virtual worlds specifically aimed for children’s development and education: (1) curriculum, (2) mentoring model, (3) diversity, (4) project scale, (5) type of contact with participants, (6) type of assessment and evaluation, (7) access environment, and (8) institutional context of usage.

The feasibility of Carbon Nanotubes for power delivery in 3-D Integrated Circuits

Increased power density and package asymmetry pose challenges in designing power delivery networks for 3-D Integrated Circuits (ICs). The increased resistivity of Cu wires due to scaling has shifted attention to alternate interconnect technologies. Continued and significant innovations in CNT manufacturing at CMOS-compatible temperatures with quality low-resistive contacts promise to enable the use of CNT as a replacement. We investigate in this paper the feasibility of using CNTs for power delivery in 3-D ICs. We evaluate the use of CNTs as Through-Silicon Vias (TSVs) and as wiring for global power delivery grids, fabricated on interposer dies. We assume the CNT interconnect has a mix of single- and multi-walled CNTs with 30% metallic nanotubes. We design a 3-D system-level comparative framework that utilizes select traces from SPEC benchmarks to evaluate improvements of CNTs over Cu. Our results emphasize how CNTs can significantly improve power delivery for 3-D integrated circuits. Using CNTs for on-chip power grid and for TSVs reduces the number of TSVs by 71% when compared to a Cu implementation. For the same substrate area dedicated to power-TSVs, CNTs improve the maximum and average IR drop by 98% and 40%, respectively. Improvements in the Ldi/dt drop are 47% and 18%, respectively.

Early Estimation of TSV Area for Power Delivery in 3-D ICs

To harness the full potential of 3-D integrated circuits, analysis tools for early design space exploration are needed. Such tools, targeting multiple design facets and cost trade-off analysis, would allow designers to arrive at major decisions regarding architecture and implementations fabrics. TSVs occupy valuable silicon real estate and neither devices nor interconnects can be formed in the area occupied by a TSV. An early estimation of total TSV area allows effective budgeting of device and interconnect resources.