Navaid Zafar Rizvi

Gain-phase mismatch correction technique for I/Q channel receiver

Every communication receiver that uses in-phase and quadrature channel signal processing technique encounters problems related to matching of gain and phase in both the channels. The gain and phase imbalances occur between Low Pass Filter and Local Oscillator used in both the channels and as a result the performance of the receivers and the quality of the received signals are degraded. The imbalances produced may cause insufficient attenuation in image frequency band leading to interference. The problem needs to be compensated. This paper represents novel architecture design and implementation of COordinate Rotation DIgital Computer (CORDIC) algorithm based Adaptive FIR filter using Trigonometric Least Mean Square (TLMS) algorithm to give a solution for correcting I/Q imbalances. The design of CORDIC in the vector rotation mode results in high system throughput due to its pipelined architecture where latency is reduced in each of the pipelined stage and finds its appropriate application in real time signal processing. The good convergence of CORDIC in the given LMS algorithm based adaptive filter facilitates in easy calculation of new filter weights.

Design of high PSRR folded cascode operational amplifier for LDO applications

This paper presents a novel CMOS folded cascode operational amplifier that leads to high PSRR and provides gain nearly equal to that of a two stage op-amp. The proposed design is implemented in GPDK 0.18μm CMOS technology. This op-amp uses a folded cascode structure in the output stage combined with the differential amplifier having PMOS input transistors to achieve good input common mode range and lower flicker noise. It has an important feature that it allows the input common mode level close to supply voltage. The proposed topology improves the PSRR of op-amp which can be used for LDO applications. Simulations using Cadence under 1.8 V show a DC gain of 72.0404 dB and a phase margin of 62.4636 degree at a unity gain bandwidth of 13.33 MHz with the power consumption smaller than 0.13 mW along with a PSRR of 72.0966 dB. The layout of the design shows that the area acquired on the chip is approximately equal to 8897.27 μm2.

Parametric analysis of a hybrid 1-bit full adder in UDSM and CNTFET technology

The basic arithmetic operation used in many VLSI circuits is addition, therefore reduction in power dissipation of 1-bit adder cell will improve the performance of most of electronic devices. Carbon nanotube field effect transistor (CNTFET) is found to be one of the most promising alternatives for MOSFET. The CNTFET is a transistor in which a carbon nanotube (CNT) is used in the channel region. In this paper we have proposed CNTFETs for designing a 1-bit Hybrid full adder circuit, from which power, delay and power delay products are calculated. This paper also presents power analysis of the seven full adder cells reported as having a low PDP (Power Delay Product), by means of speed and power consumption. These full adders were designed upon various logic styles to derive the sum and carry outputs. The existing standard full adders and the proposed hybrid full adders [1] are designed and showed with better result comparison. This paper describes how the proposed hybrid full adders [1] are better in contrast to the standard full adders and also analyses how the standard full adders are not giving faithful results. The circuit was implemented using Cadence Virtuoso tools in 180, 90, 45nm and 32nm technology. We have tested these circuit for a supply of 1.8V for 180nm, 1.2V for 90nm, 1V for 45nm and 0.8V for 32nm CNTFET technology.

Performance analysis for full adder with Zipper logic

With the shrinking technology, new systems are designed that are miniature in size and perform faster operations. Adder is a basic circuit used for the purpose of addition. In a cascade design, the output of one circuit acts as an input for the other, so delay in the propagation of the carry generated while addition is major issue in the design of adders. When the circuit is designed with any other logic the problem may arise with stored values. During pre-charge, the stored output can affect the circuit. In this paper, we propose Zipper logic for adder circuit so that it prevents any leakage due to stored charge. It also avoids the need of an additional inverter. The proposed adder is designed using cadence virtuoso at 45nm with the supply voltage of 1.2V. This improves the speed of operation by replacing inverter with N P block in alternate fashion.

CMOS low-noise amplifier for 2.4-GHz wireless receivers

This paper describes a 2.4GHz low noise amplifier (LNA) intended for use in receiver system. The design has been done in 180nm technology using CMOS. The proposed LNA uses inductive degeneration technique. This amplifier provides a forward gain of 15.72dB with a low noise figure of .307dB while drawing 6.5mW from 1.8V supply voltage. The LNA uses a transformer as load. This paper presents a detailed analysis of the used design methodology and measured results.

Class E power amplifier: Implementation and comparative analysis at 1.7GHz and 2.4GHz

The power amplifier is becoming most challenging modules to design in a wireless communication system. Also, a wireless communication is demanding multi-band transmitter and receiver, so the design to get optimum efficiency and linearity in power amplifiers in multi-band applications becomes more and more challenging day by day. As such, a lot of work has been performed to design highly efficient and linear power amplifiers. The basic class E power amplifier and the cascode circuit of the class E power amplifier has been implemented and operated at two different frequencies (1.7GHz and 2.4GHz) to see the effect on the linearity parameter of PA. The voltage supply of 2.5V has been used and the input power of 12dBm. The simulation results clearly depict the linearity of the circuit with 50 ohm load.

Evaluation of transmission line and ring oscillator interconnect model for IC applications

The ability of an item to perform a required function under stated conditions for a specified period of time. The main objective of this work is to analyze and estimate the reliability of a transmission line and thirteen stage ring oscillator as interconnects using GPDK 45 nm CMOS technology. As we know that reliability basically depends on HCI NBTI, PBTI and TDDB. Basically in this paper for the performance analysis we have analyzed the results in terms of transient response, delivered power by every component and noise analysis on different incident of time. In this work the reliability factors are done by comparing power, delay and output voltage after a specific amount of time.

Performance and reliability analysis for VLSI circuits using 45nm technology

Performance and reliability analysis tests the VLSI circuits over a prolonged period of time at different conditions. Therefore, performance and reliability of an inverter circuit and two CMOS gate interconnect circuit, a combination of two inverters connected with an RC model as an interconnect structure has been analyzed. Reliability in VLSI circuits depends on hot carrier injection, negative biasing temperature instability, positive biasing temperature instability and time-dependent gate oxide breakdown. Reliability is analyzed by comparing power, delay and output voltage. The complete analysis is done using 45nm gpdk (generic process design kit) in Cadence Virtuoso.

Low power design of asynchronous SAR ADC

In this paper 8 bit SAR ADC with input voltage of 1.2V has been designed. The schematic diagram of different sub blocks has been implemented in Cadence Virtuoso using 180nm technology. Comparator was designed so that it remains in saturation for proper operation and was implemented using differential amplifier. The comparator is the main power consuming block, so most of our effort was focused on designing this block. In order to increase the precision, the R-2R ladder network was used for implementing DAC sub block. For driving ADC, asynchronous control logic was designed using Verilog coding, so there was no need for using a clock.

Electronic model of human brain using verilog

Computers are man-made machines which work according to the given set of inputs and perform some operation on the input to generate a new set of outputs. They can be programmed to perform huge and complex task yet they lack imagination and ability to understand things. On the hand human brain is a machine which can learn new tasks by process of acquiring knowledge and understanding through thought, experience and the senses. To make computer work or think like human, human brain modeling of machine is necessary. We need to know how human brain works. The basic component of human brain is neuron, which make us think and do smart things. Brains have billions of neurons and they communicate with each other using electrical impulse. These impulses are responsible for making brain think and to have a consciousness. This paper proposes such a model of a part of the brain.