Naveed Riaz

Gender classification using image processing techniques: A survey

Classification has emerged as a leading technique for problem solution and optimization. Classification has been used extensively in several problems domains. Automated gender classification is an area of great significance and has great potential for future research. It offers several industrial applications in near future such as monitoring, surveillance, commercial profiling and human computer interaction. Different methods have been proposed for gender classification like gait, iris and hand shape. However, majority of techniques for gender classification are based on facial information. In this paper, a comparative study of gender classification using different techniques is presented. The major emphasis of this work is on the critical evaluation of different techniques used for gender classification. The comparative evaluation has highlighted major strengths and limitations of existing gender classification techniques. Taking an overview of these major problems, our research is focused on summarizing the literature by highlighting its strengths and limitations. This study also presents several areas of future research in the domain of gender classification.

Survey of MPI Implementations

High Performance Computing (HPC) provides support to run advanced application programs efficiently. Message Passing Interface (MPI) is a de-facto standard to provide HPC environment in clusters connected over fast interconnect and gigabit LAN. MPI standard itself is architecture neutral and programming language independent. C++ is widely accepted choice for implementing MPI specifications like MPICH and LAM/MPI. Apart from C++ other efforts are also carried out to implement MPI specifications using programming languages such as Java, Python and C#. Moreover MPI implementations for different network layouts such as Grid and peer-to-peer exist as well. With these many implementations providing a wide range of functionalities, programmers and users find it difficult to choose the best option to address a specific problem. This paper provides an in-depth survey of available MPI implementations in different languages and for variety of network layouts. Several assessment parameters are identified to analyze the MPI implementations along with their strengths and weaknesses.

A-JUMP, architecture for Java universal message passing

Nowadays, there is a persistent demand of greater computational power to solve complex problems. High Performance Computing (HPC) with the modern trend to multi-core clusters accentuates the importance of parallelism and multithreading. This paper presents a Java based message passing implementation, named Architecture for Java Universal Message Passing (A-JUMP). A-JUMP provides flexibility to programmers in writing parallel applications using multiple programming languages. Moreover, it also provides facility to use different network protocols for message communication. The backbone of A-JUMP is HPC bus that facilitates the development of parallel applications. It provides the interoperability between different hardware resources, communication protocols and mediums. The HPC bus is built upon well-established industry standards; Java Messaging Service (JMS) and Java programming language. In HPC bus, ActiveMQ is solely responsible for communication and message passing in an asynchronous manner. The communication layer of A-JUMP is disentangled from the rest of HPC bus implementation that ensures that any changes in communication protocol and network topology will remain transparent to the end users. The components of A-JUMP includes; Job Scheduler, Monitoring, Machine Registry, and Code Migrator/Execution other than HPC bus. In addition, it includes a set of easy to use APIs for writing MPI-like code. The results demonstrate promising performance for standard benchmarks like ping pong latency tests and embarrassingly parallel (EP) code execution. The comparison of these results with MPICH and MPJ Express are also presented.

Efficient gender classification methodology using DWT and PCA

Recognition of gender from face images has accomplished great popularity and also enlightened some new research problems. In this paper, we presented a new technique for gender classification using DWT and PCA. The technique has shown performance better than existing gender classification techniques. Experiments were carried out on standard face database used in various existing works of literature. Our proposed method provides high accuracy and is resilient to brightness changes comparison to those techniques which are in practice.

Facial expression recognition using computationally intelligent techniques

Facial expressions classification is a fast growing research area. Lots of contribution has been made in this area by researchers from fields of computer science, computer vision, artificial intelligence and psychology. There are many applications that use facial expression classification to identify the behavior, emotion, feelings and opinion of a person. Facial expression classification is not a trivial task as there are many factors that need to be accounted like low quality of images, noise, and shape/color of image. In this article, we have proposed an efficient facial expression classification scheme. In the first step, we perform some pre-processing steps like face detection and histogram equalization inorder to reduce the data dimenions and normalize the illumination effects. Then, an efficient feature extraction technique is used to extract the relevant face features. In the last step, we train and test Support Vector Machine (SVM) classifier to classify the facial expressions. Emirical results obtained using the JAFFE database suggest that the proposed technique produces impressive results by utilzing the best facial features.

AUTOMATED DEBUGGING OF VERILOG DESIGNS

In this article we report on novel insights in model-based software debugging of hardware description languages (HDLs). Todays simulation driven working process emphasizes the need for exploiting test suites not only for detecting but also for localizing the root cause of misbehavior. We discuss the modeling approaches for the various artifacts of the Verilog hardware description language (blocking and non-blocking statements, expressions, execution ordering) and present a novel model incorporating test suites. The evaluation of our approach on the well-known ISCAS89 benchmarks concerning single and double-fault diagnoses clearly indicates that incorporating test suites into the fault localization technique (and development process) considerably improves the accuracy of the obtained diagnosis candidates.

Employing test suites for verilog fault localization

This article briefly states the idea behind model-based diagnosis and its application to localizing faults in Verilog programs. Specifically this article outlines how to employ a test suite to further reduce the number of fault candidates. For this purpose, we propose the filtering approach and relate it to the concept of Ackermann constraints. Notably, our empirical results demonstrate that our novel technique considerably increases the diagnosis resolution even under presence of only a couple of test cases.

Advances in Automated Source-Level Debugging of Verilog Designs

Developing models for fault localization in HDL designs has been an active research area in recent years. Whereas research on circuit verification is typically conducted on Verilog programs, research on fault localization has recently focused on the VHDL domain. The research presented herein focuses on fault localization models for Verilog designs and thus promotes the investigation of the relationships between models for property verification and fault localization. Primarily we focus on two novel contributions. First, this article points out notable semantic differences between VHDL and Verilog models and discusses its implications for fault localizations. Secondly, we advance existing work by incorporating multiple testcases and provide first empirical results obtained from the the ISCAS 89 benchmarks indicating our novel technique’s applicability for real world designs.

Message Passing Framework for Globally Interconnected Clusters

In prevailing technology trends it is apparent that the network requirements and technologies will advance in future. Therefore the need of High Performance Computing (HPC) based implementation for interconnecting clusters is comprehensible for scalability of clusters. Grid computing provides global infrastructure of interconnecting clusters consisting of dispersed computing resources over Internet. On the other hand the leading model for HPC programming is Message Passing Interface (MPI). As compared to Grid computing, MPI is better suited for solving most of the complex computational problems. MPI itself is restricted to a single cluster. It does not support message passing over the internet to use the computing resources of different clusters in an optimal way. We propose a model that provides message passing capabilities between parallel applications over the internet. The proposed model is based on Architecture for Java Universal Message Passing (A-JUMP) framework and Enterprise Service Bus (ESB) named as High Performance Computing Bus. The HPC Bus is built using ActiveMQ. HPC Bus is responsible for communication and message passing in an asynchronous manner. Asynchronous mode of communication offers an assurance for message delivery as well as a fault tolerance mechanism for message passing. The idea presented in this paper effectively utilizes wide-area intercluster networks. It also provides scheduling, dynamic resource discovery and allocation, and sub-clustering of resources for different jobs. Performance analysis and comparison study of the proposed framework with P2P-MPI are also presented in this paper.

Biometric template security: an overview

Purpose The security of the stored biometric template is itself a challenge. Feature transformation techniques and biometric cryptosystems are used to address the concerns and improve the general acceptance of biometrics. The purpose of this paper is to provide an overview of different techniques and processes for securing the biometric templates. Furthermore, the paper explores current research trends in this area. Design/methodology/approach In this paper, the authors provide an overview and survey of different features transformation techniques and biometric cryptosystems. Findings Feature transformation techniques and biometric cryptosystems provide reliable biometric security at a high level. There are many techniques that provide provable security with practical viable recognition rates. However, there remain several issues and challenges that are being faced during the deployment of these technologies. Originality/value This paper provides an overview of currently used techniques for securing biometric templates and also outlines the related issues and challenges.