Naveen Cherukuri

Terascale chip multiprocessor memory hierarchy and programming model

Small scale chip multiprocessors are being shipped in volume by all microprocessor vendors. Many of these vendors are also investigating large scale chip multiprocessors targeted towards highly parallel workloads in media, graphics, and others. One of the most challenging aspects of architecting terascale processors is the design of a scalable memory hierarchy. Current proposals for providing coherent shared memory in terascale systems require a sophisticated coherence protocol and memory hierarchy. In this paper we propose an alternate memory configuration along with a programming model that significantly simplifies the terascale memory hierarchy. Our proposal still provides fully coherent shared memory but eliminates the hardware coherence protocol. Our programming model enables the programmer to better express the memory characteristic of terascale workloads. Finally, our proposed memory hierarchy performs better and is more scalable than conventional designs.

Run-to-run variability on Xeon Phi based cray XC systems

The increasing complexity of HPC systems has introduced new sources of variability, which can contribute to significant differences in run-to-run performance of applications. With components at various levels of the system contributing variability, application developers and system users are now faced with the difficult task of running and tuning their applications in an environment where run-to-run performance measurements can vary by as much as a factor of two to three. In this study, we classify, quantify, and present ways to mitigate the sources of run-to-run variability on Cray XC systems with Intel Xeon Phi processors and a dragonfly interconnect. We further demonstrate that the code-tuning performance observed in a variability-mitigating environment correlates with the performance observed in production running conditions.