Naveen Kaushik

Few-Layer MoS2 p-Type Devices Enabled by Selective Doping Using Low Energy Phosphorus Implantation

P-type doping of MoS2 has proved to be a significant bottleneck in the realization of fundamental devices such as p-n junction diodes and p-type transistors due to its intrinsic n-type behavior. We report a CMOS compatible, controllable and area selective phosphorus plasma immersion ion implantation (PIII) process for p-type doping of MoS2. Physical characterization using SIMS, AFM, XRD and Raman techniques was used to identify process conditions with reduced lattice defects as well as low surface damage and etching, 4X lower than previous plasma based doping reports for MoS2. A wide range of nondegenerate to degenerate p-type doping is demonstrated in MoS2 field effect transistors exhibiting dominant hole transport. Nearly ideal and air stable, lateral homogeneous p-n junction diodes with a gate-tunable rectification ratio as high as 2 × 10(4) are demonstrated using area selective doping. Comparison of XPS data from unimplanted and implanted MoS2 layers shows a shift of 0.67 eV toward lower binding energies for Mo and S peaks indicating p-type doping. First-principles calculations using density functional theory techniques confirm p-type doping due to charge transfer originating from substitutional as well as physisorbed phosphorus in top few layers of MoS2. Pre-existing sulfur vacancies are shown to enhance the doping level significantly.

Schottky barrier heights for Au and Pd contacts to MoS2

The search of a p-type metal contact on MoS2 has remained inconclusive, with high work function metals such as Au, Ni, and Pt showing n-type behavior and mixed reports of n as well as p-type behavior for Pd. In this work, we report quantitative Schottky barrier heights for Au and Pd contacts to MoS2 obtained by analysing low temperature transistor characteristics and contact resistance data obtained using the transfer length method. Both Au and Pd exhibit n-type behavior on multilayer as well as monolayer MoS2 transistors with Schottky barrier heights of 0.126 eV and 0.4 eV, and contact resistances of 42 Ω.mm and 18 × 104 Ω.mm respectively. Scanning photocurrent spectroscopy data is in agreement with the resulting energy band alignment in Au-MoS2-Pd devices further reinforcing the observation that the Fermi-level is pinned in the upper half of MoS2 bandgap.

Interfacial n-Doping Using an Ultrathin TiO2 Layer for Contact Resistance Reduction in MoS2

We demonstrate a low and constant effective Schottky barrier height (ΦB ∼ 40 meV) irrespective of the metal work function by introducing an ultrathin TiO2 ALD interfacial layer between various metals (Ti, Ni, Au, and Pd) and MoS2. Transmission line method devices with and without the contact TiO2 interfacial layer on the same MoS2 flake demonstrate reduced (24×) contact resistance (RC) in the presence of TiO2. The insertion of TiO2 at the source-drain contact interface results in significant improvement in the on-current and field effect mobility (up to 10×). The reduction in RC and ΦB has been explained through interfacial doping of MoS2 and validated by first-principles calculations, which indicate metallic behavior of the TiO2-MoS2 interface. Consistent with DFT results of interfacial doping, X-ray photoelectron spectroscopy (XPS) data also exhibit a 0.5 eV shift toward higher binding energies for Mo 3d and S 2p peaks in the presence of TiO2, indicating Fermi level movement toward the conduction band (n-type doping). Ultraviolet photoelectron spectroscopy (UPS) further corroborates the interfacial doping model, as MoS2 flakes capped with ultrathin TiO2 exhibit a reduction of 0.3 eV in the effective work function. Finally, a systematic comparison of the impact of selective doping with the TiO2 layer under the source-drain metal relative to that on top of the MoS2 channel shows a larger benefit for transistor performance from the reduction in source-drain contact resistance.

Thickness tunable transport in alloyed WSSe field effect transistors

We report the field effect transistor characteristics of exfoliated transition metal dichalcogenide alloy tungsten sulphoselenide. WSSe is a layered material of strongly bonded S-W-Se atoms having weak interlayer van der Waals forces with a significant potential for spintronic and valleytronic applications due to its polar nature. The X-ray photoelectron spectroscopy measurements on crystals grown by the chemical vapor transport method indicate a stoichiometry of the form WSSe. We report flake thickness tunable transport mechanism with n-type behavior in thin flakes ( ≤11 nm) and ambipolarity in thicker flakes. The devices with flake thicknesses of 2.4 nm–54.8 nm exhibit a maximum electron mobility of ∼50 cm2/V s along with an ION/IOFF ratio >106. The electron Schottky barrier height values of 35 meV and 52 meV extracted from low temperature I–V measurements for 3.9 nm and 25.5 nm thick flakes, respectively, indicate that an increase in hole current with thickness is likely due to lowering of the bandgap ...

Reversible hysteresis inversion in MoS2 field effect transistors

The origin of threshold voltage instability with gate voltage in MoS2 transistors is poorly understood but critical for device reliability and performance. Reversibility of the temperature dependence of hysteresis and its inversion with temperature in MoS2 transistors has not been demonstrated. In this work, we delineate two independent mechanisms responsible for thermally assisted hysteresis inversion in gate transfer characteristics of contact resistance-independent multilayer MoS2 transistors. Variable temperature hysteresis measurements were performed on gated four-terminal van der Pauw and two-terminal devices of MoS2 on SiO2. Additional hysteresis measurements on suspended (~100 nm air gap between MoS2 and SiO2) transistors and under different ambient conditions (vacuum/nitrogen) were used to further isolate the mechanisms. Clockwise hysteresis at room temperature (300 K) that decreases with increasing temperature is shown to result from intrinsic defects/traps in MoS2. At higher temperatures a second, independent mechanism of charge trapping and de-trapping between the oxide and p+ Si gate leads to hysteresis collapse at ~350 K and anti-clockwise hysteresis (inversion) for temperatures >350 K. The intrinsic-oxide trap model has been corroborated through device simulations. Further, pulsed current–voltage (I–V) measurements were carried out to extract the trap time constants at different temperatures. Non-volatile memory and temperature sensor applications exploiting temperature dependent hysteresis inversion and its reversibility in MoS2 transistors have also been demonstrated.MoS 2 devices: variable temperature measurements unveil reversible hysteresis mechanismsDefects and traps in MoS2 van der Pauw devices give rise to a hysteresis inversion mechanism which is reversible with temperature. A team led by Saurabh Lodha at the Indian Institute of Technology Bombay performed variable temperature hysteresis measurements on four- and two-terminal MoS2 devices, both suspended and supported on a SiO2 substrate. The onset of a clockwise hysteresis at room temperature was attributed to intrinsic MoS2 defects, whereas an additional mechanism resulting in an anticlockwise hysteresis was observed at higher temperature, and attributed to extrinsic charge trapping and de-trapping between the oxide and the silicon gate. By leveraging the temperature dependence of the hysteresis in MoS2, the authors developed a non-volatile memory and a temperature sensor.

Contact resistance reduction in MoS 2 FETs using ultra-thin TiO 2 interfacial layers

High contact resistance (R_C) at metal-Molybdenum disulfide (MoS₂) interface obscures the intrinsic transport properties of MoS₂ [1] and limits its potential as a channel material for future CMOS technology. In this work, we report reduction in the effective Schottky barrier height (SBH) and contact resistance at the metal-MoS₂ interface using an ultra-thin TiO₂ interfacial layer (IL) resulting in higher (upto 11X) field-effect mobility. Our results show, not only a reduction (upto 10X) but also a nearly constant (~40 meV) SBH irrespective of the metal work function, unlike Ge/Si where TiO₂ unpins the Fermi-level [2]. XPS and UPS measurements suggest that low RC and constant effective SBH can be attributed to charge transfer at the TiO₂-MoS₂ interface such that the MoS₂ layer near the interface is doped n-type. Additional improvement in MoS₂ FET performance is demonstrated by using TiO₂ as a dielectric on top of the MoS₂ channel.

P-type doping of MoS 2 with phosphorus using a plasma immersion ion implantation (PIII) process

A controllable and area selective doping process, especially for p-type Molybdenum disulphide (MoS2), is essential for the realization of various p/n junction-based devices. In this work, we demonstrate p-type doping of multilayer MoS2 with phosphorus (P) as a dopant using a CMOS-compatible plasma immersion ion implantation (PIII) technique. Detailed physical characterization including XPS and SIMS, backed with ab-initio DFT calculations, confirms p-type doping in P-implanted MoS2 that could be due to a combination of surface charge transfer from physisorbed phosphine ions and/or substitutional phosphorus present in the top few (~5) layers. Controlled reduction in current levels and positive VT shifts were observed in channel-doped MoS2 transistors. Further, selectively doped gated p/n-junction diodes (rectification ~50X) have been demonstrated.

Evaluating Au and Pd contacts in mono and multilayer MoS 2 transistors

The search of a p-type metal contact on MoS₂ has remained inconclusive, with high work-function metals such as Au, Ni and Pt showing n-type behavior [1] and mixed reports of n as well as p-type behavior for Pd. In this work we report for the first time, quantitative band alignment of Pd and Au-MoS₂ interfaces using low temperature and scanning photocurrent measurements on MoS₂ transistors with varying metal contacts (Au-Au, Pd-Pd and Au-Pd). Our results indicate n-type behavior for Pd contacts on multilayer as well as monolayer MoS₂ transistors and a barrier height (Φ_b) of nearly 0.5 eV, four times that for Au contacts indicating that the MoS₂ Fermi-level is pinned in the upper half of MoS₂ bandgap.

Multilayer ReS2 Photodetectors with Gate Tunability for High Responsivity and High Speed Applications

Rhenium disulfide (ReS2) is an attractive candidate for photodetection applications owing to its thickness-independent direct band gap. Despite various photodetection studies using two-dimensional semiconductors, the trade-off between responsivity and response time under varying measurement conditions has not been studied in detail. This report presents a comprehensive study of the architectural, laser power and gate bias dependence of responsivity and speed in supported and suspended ReS2 phototransistors. Photocurrent scans show uniform photogeneration across the entire channel because of enhanced optical absorption and a direct band gap in multilayer ReS2. A high responsivity of 4 A W-1 (at 50 ms response time) and a low response time of 20 μs (at 4 mA W-1 responsivity) make this one of the fastest reported transition-metal dichalcogenide photodetectors. Occupancy of intrinsic (bulk ReS2) and extrinsic (ReS2/SiO2 interface) traps is modulated using gate bias to demonstrate tunability of the response time (responsivity) over 4 orders (15×) of magnitude, highlighting the versatility of these photodetectors. Differences in the trap distributions of suspended and supported channel architectures, and their occupancy under different gate biases enable switching the dominant operating mechanism between either photogating or photoconduction. Further, a new metric that captures intrinsic photodetector performance by including the trade-off between its responsivity and speed, besides normalizing for the applied bias and geometry, is proposed and benchmarked for this work.

Suspended ReSi FET for improved photocurrent-time response

Strong light-matter interaction in 2D transition metal dichalcogenides (TMDs) presents a significant opportunity for many optoelectronic applications [1-7]. In photodetector devices, the transit time of photogenerated carriers is limited by their mobility, which affects the photoconductive gain and response time of the device. In this work, we report significant improvement in photocurrent-time response of few layer suspended ReS2-based FETs under broad laser beam illumination. High carrier life time in ReS2 results from the presence of traps [1, 2]. Suspended ReS2 devices have less interface defects [5] as compared to supported (on SiO2) transistors, which helps reduce the life time of the photogenerated carriers [1] and hence improve the photocurrent-time response of the device. Further, improved mobility in the suspended devices due to fewer interface traps also helps to enhance the photocurrent-time response.