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Dive into the research topics where Naveen Verma is active.

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Featured researches published by Naveen Verma.


Nano Letters | 2013

3D Printed Bionic Ears

Manu Sebastian Mannoor; Ziwen Jiang; Teena James; Yong Lin Kong; Karen Malatesta; Winston O. Soboyejo; Naveen Verma; David H. Gracias; Michael C. McAlpine

The ability to three-dimensionally interweave biological tissue with functional electronics could enable the creation of bionic organs possessing enhanced functionalities over their human counterparts. Conventional electronic devices are inherently two-dimensional, preventing seamless multidimensional integration with synthetic biology, as the processes and materials are very different. Here, we present a novel strategy for overcoming these difficulties via additive manufacturing of biological cells with structural and nanoparticle derived electronic elements. As a proof of concept, we generated a bionic ear via 3D printing of a cell-seeded hydrogel matrix in the precise anatomic geometry of a human ear, along with an intertwined conducting polymer consisting of infused silver nanoparticles. This allowed for in vitro culturing of cartilage tissue around an inductive coil antenna in the ear, which subsequently enables readout of inductively-coupled signals from cochlea-shaped electrodes. The printed ear exhibits enhanced auditory sensing for radio frequency reception, and complementary left and right ears can listen to stereo audio music. Overall, our approach suggests a means to intricately merge biologic and nanoelectronic functionalities via 3D printing.


IEEE Journal of Solid-state Circuits | 2008

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

Naveen Verma; Anantha P. Chandrakasan

Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit significantly from an SRAM that offers read and write functionality at the lowest possible voltage. However, bit-cells and architectures achieving very high density conventionally fail to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used to ensure read stability, and peripheral control of both the bit-cell supply voltage and the read-buffers foot voltage enable sub-T4 write and read without degrading the bit-cells density. The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy, which reduces read errors by a factor of five compared to device up-sizing. At its lowest operating voltage, the entire 256 kb SRAM consumes 2.2 muW in leakage power.


Nature Communications | 2012

Graphene-based wireless bacteria detection on tooth enamel

Manu Sebastian Mannoor; Hu Tao; Jefferson D. Clayton; Amartya Sengupta; David L. Kaplan; Rajesh R. Naik; Naveen Verma; Fiorenzo G. Omenetto; Michael C. McAlpine

Direct interfacing of nanosensors onto biomaterials could impact health quality monitoring and adaptive threat detection. Graphene is capable of highly sensitive analyte detection due to its nanoscale nature. Here we show that graphene can be printed onto water-soluble silk. This in turn permits intimate biotransfer of graphene nanosensors onto biomaterials, including tooth enamel. The result is a fully biointerfaced sensing platform, which can be tuned to detect target analytes. For example, via self-assembly of antimicrobial peptides onto graphene, we show bioselective detection of bacteria at single-cell levels. Incorporation of a resonant coil eliminates the need for onboard power and external connections. Combining these elements yields two-tiered interfacing of peptide-graphene nanosensors with biomaterials. In particular, we demonstrate integration onto a tooth for remote monitoring of respiration and bacteria detection in saliva. Overall, this strategy of interfacing graphene nanosensors with biomaterials represents a versatile approach for ubiquitous detection of biochemical targets.


international solid-state circuits conference | 2008

A 65nm Sub-V t Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter

Joyce Kwong; Yogesh K. Ramadass; Naveen Verma; Markus Koesler; Korbinian Huber; Hans Moormann; Anantha P. Chandrakasan

This paper presents a 65nm sub-Vt SoC featuring a microcontroller core and custom 128Kb SRAM functional in sub-threshold, powered by a switched capacitor DC-DC converter that delivers variable load voltages from 0.3V to 0.6V.


IEEE Journal of Solid-state Circuits | 2007

An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes

Naveen Verma; Anantha P. Chandrakasan

A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 muW from a 1-V supply. The ADCs CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by self-timing the bit-decisions. Prototyped in a 0.18-mum, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively


IEEE Transactions on Computers | 2005

Design considerations for ultra-low energy wireless microsensor nodes

Benton H. Calhoun; Denis C. Daly; Naveen Verma; Daniel Frederic Finchelstein; David D. Wentzloff; Alice Wang; Seong Hwan Cho; Anantha P. Chandrakasan

This tutorial paper examines architectural and circuit design techniques for a microsensor node operating at power levels low enough to enable the use of an energy harvesting source. These requirements place demands on all levels of the design. We propose architecture for achieving the required ultra-low energy operation and discuss the circuit techniques necessary to implement the system. Dedicated hardware implementations improve the efficiency for specific functionality, and modular partitioning permits fine-grained optimization and power-gating. We describe modeling and operating at the minimum energy point in the subthreshold region for digital circuits. We also examine approaches for improving the energy efficiency of analog components like the transmitter and the ADC. A microsensor node using the techniques we describe can function in an energy-harvesting scenario.


Annual Review of Biomedical Engineering | 2008

Ultralow-Power Electronics for Biomedical Applications

Anantha P. Chandrakasan; Naveen Verma; Denis C. Daly

The electronics of a general biomedical device consist of energy delivery, analog-to-digital conversion, signal processing, and communication subsystems. Each of these blocks must be designed for minimum energy consumption. Specific design techniques, such as aggressive voltage scaling, dynamic power-performance management, and energy-efficient signaling, must be employed to adhere to the stringent energy constraint. The constraint itself is set by the energy source, so energy harvesting holds tremendous promise toward enabling sophisticated systems without straining user lifestyle. Further, once harvested, efficient delivery of the low-energy levels, as well as robust operation in the aggressive low-power modes, requires careful understanding and treatment of the specific design limitations that dominate this realm. We outline the performance and power constraints of biomedical devices, and present circuit techniques to achieve complete systems operating down to power levels of microwatts. In all cases, approaches that leverage advanced technology trends are emphasized.


IEEE Transactions on Electron Devices | 2008

Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits

Naveen Verma; Joyce Kwong; Anantha P. Chandrakasan

Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.


IEEE Journal of Solid-state Circuits | 2009

A 65 nm Sub-

Joyce Kwong; Yogesh K. Ramadass; Naveen Verma; Anantha P. Chandrakasan

Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V DD of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power.


international solid-state circuits conference | 2007

V_{t}

Naveen Verma; Anantha P. Chandrakasan

A 65nm 256kb 8T SRAM operates in sub-V, at 350mV. Peripheral assists eliminate sub-V, bitline leakage without limiting read current, and for a given area, sense-amplifier redundancy reduces read errors from offsets by a factor of five compared with device upsizing.

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Anantha P. Chandrakasan

Massachusetts Institute of Technology

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