Nazrul Anuar Nayan

LSI implementation of a low-power 4 × 4-bit array two-phase clocked adiabatic static CMOS logic multiplier

As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development-of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity are common approaches used in conventional CMOS. In adiabatic switching circuits, the current flow through transistors can be significantly reduced by ensuring uniform charge transfer over the entire available time. This paper presents the simulation of this current in two-phase clocked adiabatic static CMOS logic (2PASCL) and conventional CMOS. From the SPICE simulations, at transition frequencies from 1 to 12MHz, a 4x4-bit array 2PASCL multiplier shows a maximum reduction in power dissipation of 77% relative to that of a static CMOS. The measurement results of a 4x4-bit array 2PASCL multiplier demonstrate a 57% reduction compared to a 4x4-bit array two-phase clocked adiabatic dynamic CMOS logic (2PADCL). These results indicate that 2PASCL technology can be advantageous when applied to low-power digital devices operated at low frequencies, such as radio-frequency identification (RFID) tags, smart cards, and sensors.

FPGA design and implementation of Electrocardiogram biomedical embedded system

This paper presents a FPGA design and implementation of Electrocardiogram (ECG) biomedical embedded system (ECG-SoC). It performs ECG pre-processing and heart rate variability (HRV) feature extraction which suitable for remote homecare monitoring and rural health care application. The ECG-SoC is designed using hardware/software co-design technique based on offline dataset from MIT-BIH database. Altera Cyclone II DE2-115 FPGA platform was used for system prototyping and functionality verification. The computation results are displayed on Nios II-Linux terminal and produce output files for post analysis executed on the host personal computer (PC).

Power-saving analysis of adiabatic logic in subthreshold region

This paper reports a comparison of energy dissipation between different adiabatic logics in the subthreshold operation. In SPICE simulation we use a real industrial 0.18 μm BSIM3v3 model having a device parameter in the subthreshold region and then confirm the energy savings of quasi-adiabatic logic families, namely, 2N2N2P, 2PC2AL, CAL, ECRL, PAL, PECRL, PFAL, and SAL. From the results we show that the energy consumption of our previously proposed 2PC2AL inverter is lower than those of the other adiabatic logics, in the range of from 10 kHz to 10 MHz.

A low-power sense amplifier for adiabatic memory using memristor

This paper proposes a sense amplifier for adiabatic memory using memristor. The proposed sense amplifier uses current rate sensing method. In simulation the proposed sense amplifier is to connect the content addressable memory (CAM) with adiabatic driving. From the results we show that the proposed circuit is correctly operated and its power dissipation is 36.1 pJ/cycle.

2PCDAL: Two-phase clocking dual-rail adiabatic logic

This paper presents a new dual-rail adiabatic logic which called 2PCDAL. Our proposed circuit is based on 2N2N2P structure. Unlike 2N2N2P which is driven by four-phase clocking, the proposed logic only needs two-phase clocking to operate. Compared with the proposed 2PCDAL and the other dual-rail quasi-adiabatic logic families of cell design, namely, 2N2N2P, CAL, ECRL, PAL, and PFAL, we show that the energy consumption of the proposed 2PCDAL inverter is almost the same as those of the other dual-rail adiabatic logics (i.e. 2N2N2P, ECRL, and PFAL) in the range of from 10 kHz to 10 MHz.

PVDF sensor design and FPGA implementation of ultrasound power measurement

Ultrasound devices provide either diagnostic or therapeutic purpose in biomedical application. To avoid unwanted power exposure to the patient for safety concern but at the same time maintaining optimum diagnostic and therapeutic effect, ultrasound power meter is used to measure and calibrate the output power and intensity of the ultrasound machine. Most of the current ultrasound power meters are limited for either high power therapeutic or low power diagnostic purposes but not both and it is expensive. To enable Polyvinylidene fluoride (PVDF) for low cost ultrasound power meter, a robust low cost casing has been designed for optimum ultrasound power capturing from both therapeutic and diagnostic ultrasound machine. The system has been designed to minimize interference effect and noise, as well as to stabilize mechanical construction of the sensor. This paper presents a PVDF sensor design of an ultrasound power measurement system that is compact and simple in construction, easy and user friendly, but at the same time provides a reliable power measurement result. The power meter is designed using PVDF sensor and Altera Cyclone II Field Programmable Gate Array (FPGA) technology. Results show that this in-house power measurement system is able to measure 0.5 MHz - 10 MHz of the frequency range and 1 mW/cm2 to 10 W/cm2 of the intensity range.