Nelson Nazzicari

An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation Algorithm

Biometric identification systems are defined as systems exploiting automated methods of personal recognition based on physiological or behavioural characteristics. Among these, fingerprints are very reliable biometric identifiers. Trying to fasten the image processing step makes the recognition process more efficient, especially concerning embedded systems for real-time authentication. In this paper we propose an FPGA-based architecture that efficiently implements the high computationally demanding core of a matching algorithm based on phase-only spatial correlation. Moreover, we show how it is possible to use COTS components to embed an entire AFIS on chip and so reducing cost, space and energy used.

An Accelerator for Physics Simulations

An accelerator based on field-programmable gate array (FPGA) technology accelerates double-precision floating-point operations present in the energy calculation of Monte Carlo-Metropolis simulations. The accelerator uses COTS components and is scalable in terms of clock frequency, memory capability, and number of computing units. It could also be part of a cluster of accelerated workstations.

An embedded multi-core biometric identification system

Biometric identification systems exploit automated methods of recognition based on physiological or behavioural characteristics. Among these, fingerprints are very reliable as biometric identifiers. In order to build embedded systems performing real-time authentication, a fast computational unit for image processing is required. In this paper we propose a parallel architecture that efficiently implements the high computationally demanding core of a matching algorithm based on Band-Limited Phase Only spatial Correlation (BLPOC), performed by two concurrent computational units implemented onto a Stratix II Altera family FPGA. The device here described is competitive with similar hardware solutions described in literature and outperforms the elaboration capabilities of general-purpose processors.

A Multicore Embedded Processor for Fingerprint Recognition

Biometric identification systems exploit automated methods of recognition based on physiological or behavioural people characteristics. Among these, fingerprints are very affordable biometric identifiers. In order to build embedded systems performing real-time authentication, a fast computational unit for image processing is required. In this paper we propose a parallel architecture that efficiently implements the high computationally demanding core of a matching algorithm based on Band Limited Phase Only spatial Correlation (BLPOC), elaborated by two concurrent computational units implemented onto Stratix II family Altera FPGA. The realised device is competitive with those provided by similar hardware solutions described in literature and outperforms the elaboration capabilities of general purpose PC processors.

An Embedded Acquisition System for Remote Monitoring of Tire Status in F1 Race Cars through Thermal Images

One of the most critical performance factors for race car is tires management. In particular, the main factor which provides information about the workload of tires is the temperature. Until now, the race engineerpsilas knowledge of how the tires performed has traditionally been limited to temperature readings, manually taken when the car returns to the pits. It does not provide the engineer with any real idea about how the tires are working at a specific part of the track on any specific lap. Having a better knowledge about how the tires work could offer an important advantage that allows to get to extremely pointy setups. To optimize the tire use, a more accurate way of monitoring their temperatures is presented: in this paper we introduce a new approach to study the tire temperature that use an infrared camera to effectively know how it evolves.

A Dedicated Hardware for Fingerprint Authentication

Biometric systems are defined as systems exploiting automated methods of personal recognition based on physiological or behavioural characteristics. Among these, fingerprints are very reliable biometric identifiers. Trying to fasten the image processing step makes the recognition process more efficient, especially concerning embedded systems for real-time authentication. In this work we propose an FPGA-based architecture that efficiently implements the high computationally demanding core of a matching algorithm.

Lab on Chip: Portable Optical Device for On-site Multi-parametric Analysis

Recently the demand dramatically grew up for portable biosensors, providing an on-site multi-parametric measurement. Present instruments, however, are limited by large size and consumption (which prevents portability) and costs (which prevents their usage in some Countries). In this paper, we propose a compact and portable device based on a nano-structured array biochip featuring the Surface Plasmonic Resonance, lighted by a suitable optics and equipped with an 830 nm irradiating LED. The reflected image is detected by an Aptina CMOS sensor and managed by an ARM9 processor which is responsible of the acquisition end processing, performed within 14 sec form the application of the assy. The processor evaluates the average grey level pixel ratio between suitable biochip areas so as to be independent on illumination fluctuations and external noise. Preliminary results indicate a sensitivity close to 10-4 RIU change in the refractive index and applicability of the device to different applications and fields (waste water and food pollution analysis, among the main ones).

A Video Elaboration System for Image Deinterlacing and Processing in Race Cars

Today, video cameras are a very common way to gather data from physical processes also thanks to the technological evolution, seen both for the acquisition devices and the visualization/elaboration ones, which brought high quality at low costs. The video world, unfortunately, still suffers from the legacies of the early analog video era, so that engineers often have to deal with artifacts whose presence is only related to the will of remaining compatible with such old video technologies, among which the interlacement is certainly one of the most problematic ones. In this letter, we will present a work, in collaboration with the Magneti Marelli Motorsport division, aimed at developing a video acquisition system to be installed on F1 race cars for tire or wing monitoring, together with a low-cost field-programmable gate array (FPGA)-based video deinterlacer, which would allow them to use analog cameras whenever they are unable to use a digital one.

An Application Specific Processor for Montecarlo Simulations

In this paper we describe an accelerator based on FPGA technology and interfaced to an external host computing system through standard bus connections; it is conceived to accelerate double precision floating point operations, present in the energy calculation of Monte Carlo (MC) metropolis particle system simulations. The accelerator plays the role of coprocessor giving a speed-up factor equal to 4, with respect last generation PCs. The proposed solution is based on COTS components and shows good characteristics of scalability in terms of clock frequency, memory capability and number of computing units. Moreover, the accelerator can be also conceived as a part of a computing system made up by a cluster of accelerated workstations

High performance computing through SoC coprocessors

In this paper we describe DPFPA (Double Precision Floating Point Accelerator), a FPGA-based coprocessor interfaced to the CPU through standard bus connections; it is conceived to accelerate double precision floating point operations, featuring two double precision floating point units, a pipelined adder and a pipelined multiplier with a suitable number of stages. We tested its performance by implementing a Montecarlo-Metropolis simulation of a dipolar system, using a proper software development environment designed and realized in our laboratory. DPFPA can provide a speed-up equal to 4, with respect last generation PC, showing also a good scalability in terms of clock frequency, memory capability and number of computing units.