Nevine AbouGhazaleh

Toward the placement of power management points in real-time applications

Dynamically changing CPU voltage and frequency has been shown to greatly save the processor energy. These adjustments can be done at specific power management points (PMPs), which are not without overheads. In this work we study the effect of different overheads on both time and energy; these can be seen as the overhead of computing the new speed, and then the overhead of dynamically adjusting the speed. We propose a theoretical solution for choosing the granularity of inserting PMPs in a program taking into consideration such overheads. We validate our theoretical results and show that the accuracy of the theoretical model is very close to the simulations we carry out.

Energy management for real-time embedded applications with compiler support

Reducing device energy has become one of the most important challenges to embedded systems designers. Processors with dynamic voltage scaling permit trading performance for reduced energy consumption as a program executes. In this paper, we first present a novel hybrid scheme that uses dynamic voltage scaling to adjust the performance of embedded applications to reduce energy consumption while also meeting time constraints. Our fine grained approach uses the compiler to insert power management hints in the application code. These hints convey path specific run-time information about the programs progress to power management points invoked by the operating system that adjust processor performance. Second we present an algorithm for inserting power management hints along different program paths. Finally, we experimentally evaluate our approach and show that signi cant energy reduction can be achieved. On two embedded applications, MPEG movie decoding and automatic target recognition, our scheme reduces energy by up to 79% over no power management and by up to over 50% static power management. We also experimentally demonstrate that our scheme achieves more energy savings compared to two purely compiler directed schemes.

Power aware scheduling for AND/OR graphs in multiprocessor real-time systems

Power aware computing has become popular recently and many techniques have been proposed to manage the energy consumption for traditional real-time applications. We have previously proposed (2001) two greedy slack sharing scheduling algorithms for such applications on multi-processor systems. In this paper, we are concerned mainly with real-time applications that have different execution paths consisting of different number of tasks. The AND/OR graph model is used to represent the application data dependence and control flow. The contribution of this paper is twofold. First, we extend our greedy slack sharing algorithm for traditional applications to deal with applications represented by AND/OR graphs. Then, using the statistical information about the applications, we propose a few variations of speculative scheduling algorithms that intend to save energy by reducing the number of speed changes (and thus the overhead) while ensuring that the applications meet the timing constraints. The performance of the algorithms is analyzed with respect to energy savings. The results obtained show that the greedy scheme is better than some speculative schemes and that the greedy scheme is good enough when a reasonable minimal speed exists in the system.

Power management points in power-aware real-time systems

Managing power consumption while simultaneously delivering acceptable levels of performance is becoming a critical issue in several application domains such as wireless computing. We integrate compiler-assisted techniques with power-aware operating system services and present scheduling techniques to reduce energy consumption of applications that have deadlines. We show by simulation that our dynamic power management schemes dramatically decrease energy consumption.

Dynamic rate-selection for extending the lifetime of energy-constrained networks

Wireless networks have a constraint on their functional lifetime. This is due to the limited energy capacity of batteries powering the wireless nodes. For extending the lifetime of such battery-operated networks, we present a scheme for dynamically selecting the transmission rate for each node in the network. The transmission rate is based on the available energy budget in each nodes battery. The goal is to increase the network capability of delivering more packets. The rate selection for each node is subject to satisfying a QoS timing constraint on the packet delivery time. Through adaptively varying each nodes rate, we extended the lifetime 10 times on average more transmitting at a maximum rate and delivered on average 7.5 times more data packets. When compared with a scheme that transmits data at a lower rates independent of the battery levels, our scheme delivers up to 12% more packets for the same available total energy.

Integrated CPU and l2 cache voltage scaling using machine learning

Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applications. Unfortunately, adding more resources typically comes on the expense of higher energy costs. New chip design with Multiple Clock Domains (MCD) opens the opportunity for fine-grain power management within theprocessor chip. When used with dynamic voltage scaling (DVS), we can control the voltage and power of each domain independently. A significant power and energy improvement has been shown when using MCD design in comparison to managing a single voltage domain for the whole chip, as in traditional chips with global DVS. In this paper, we propose PACSL a Power-Aware Compiler-based approach using Supervised Learning. PACSL automatically derives an integrated CPU-core and on-chip L2 cache DVS policy tailored to a specific system and workload. Our approach uses supervised machine learning to discover a policy, which relies on monitoring a few performance counters. We present our approach detailing the role of a compiler in constructing a custom power management policy. We also discuss some implementation issues associated with our technique. We show that PACSL improves on traditional power management techniques that are used in general MCD chips. Our technique saves 22% on average (up to 46%) in energy-delay product over a DVS technique that applies independent DVS decisions in each domain. Compared to no-power management, our technique improves energy-delay product by 26% on average (up to 64%).

Near-memory caching for improved energy consumption

The main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a power-aware cached-dynamic-RAM (PA-CDRAM) organization that integrates a moderately sized cache directly into a memory chip. We use this near-memory cache to turn a memory bank off immediately after it is accessed to reduce power consumption. We modify the operation and structure of CDRAM with the goal of reducing energy consumption while retaining the performance advantage for which CDRAM was originally proposed. In this paper, we describe our PA-CDRAM organization and show how to incorporate it into the Rambus memory. We evaluate the approach using a cycle-accurate processor and memory simulator. Our results show that PA-CDRAM achieves up to 84 percent (28 percent on the average) improvement in the energy-delay product and up to 76 percent (19 percent on the average) savings in energy when compared to a time-out power management technique.

Integrated CPU cache power management in multiple clock domain processors

Multiple clock domain (MCD) chip design addresses the problem of increasing clock skew in different chip units. Importantly, MCD design offers an opportunity for fine grain power/energy management of the components in each clock domain with dynamic voltage scaling (DVS). In this paper, we propose and evaluate a novel integrated DVS approach to synergistically manage the energy of chip components in different clock domains. We focus on embedded processors where core and L2 cache domains are the major energy consumers. We propose a policy that adapts clock speed and voltage in both domains based on each domains workload and the workload experienced by the other domain. In our approach, the DVS policy detects and accounts for the effect of inter-domain interactions. Based on the interaction between the two domains, we select an appropriate clock speed and voltage that optimizes the energy of the entire chip. For the Mibench benchmarks, our policy achieves an average improvement over no-power-management of 15.5% in energy-delay product and 19% in energy savings. In comparison to a traditional DVS policy for MCD design that manages domains independently, our policy achieves an 3.5%average improvement in energy-delay and 4% less energy, with a negligible 1% decrease in performance. We also show that an integrated DVS policy for MCD design with two domains is more energy efficient for simple embedded processors than high-end ones.

Near-Memory Caching for Improved Energy Consumption

The main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a power-aware cached-dynamic-RAM (PA-CDRAM) organization that integrates a moderately sized cache directly into a memory chip. We use this near-memory cache to turn a memory bank off immediately after it is accessed to reduce power consumption. We modify the operation and structure of CDRAM with the goal of reducing energy consumption while retaining the performance advantage for which CDRAM was originally proposed. In this paper, we describe our PA-CDRAM organization and show how to incorporate it into the Rambus memory. We evaluate the approach using a cycle-accurate processor and memory simulator. Our results show that PA-CDRAM achieves up to 84 percent (28 percent on the average) improvement in the energy-delay product and up to 76 percent (19 percent on the average) savings in energy when compared to a time-out power management technique.

Power management in external memory using PA-CDRAM

Main memory is one of the major energy consumers in computing systems. In this paper, we propose a new memory organisation, called Power-Aware Cached-DRAM (PA-CDRAM) that integrates a moderately sized cache directly into a memory device. We use this cache to turn memory banks off immediately after memory accesses to reduce energy consumption. We modify CDRAM (originally optimised for performance) to reduce energy consumption. We describe our memory organisation, the challenges for achieving low energy consumption and how to address them. Results show that PA-CDRAM achieves 28% average improvement in energy-delay when compared to traditional memory employing time-out power management.