Nguyen Tien Dzung

Extraction of human facial features based on Haar feature with Adaboost and image recognition techniques

Locating facial feature in face images is an important stage for numerous facial image applications such as face recognition, face expression recognition and face tracking and lip reading. In this paper, we present a robust method for detecting facial feature points in frontal face images. The method adopts face detection algorithm of Viola-Jones face detector. The facial regions are than extracted by applying Haar feature based Adaboost algorithm for detecting eye, nose and mouth regions. Finally, template matching and several image processing techniques are utilized to detect feature points. Experiment on the IMM database, CVL database and our laboratory database is carried out to demonstrate and verify the proposed method.

Efficient determination of disparity map from stereo images with modified sum of absolute differences (SAD) algorithm

This paper proposes modification of the conventional Sum of Absolute Differences (SAD) for performance improvement in depth-map estimation from stereo images captured by a camera in a stereo system. The conventional SAD is commonly search in whole stereo images to find out the difference in pixels between the left and right captured images, and then obtains the corresponding disparity map and this may lead to high elapsing time. In order to reduce the number of searching pixels, the proposed modified SAD tries to estimate the difference only from edge pixels which are referred as pixels-of-interest and bring significant information about depth map. The number of pixels being searched is reduced to about 17% on the total pixels, hence the total elapsing time is saved up to around 89% compared to that of the conventional SAD. This results is promising for implementation of a real-time vision system.

Low cost in-flow traffic monitor for South-East Asia

Safety and congestion are two factors which have driven developed countries to adopt Intelligent Transportation Systems (ITS). Such systems cannot be successfully applied to South East Asian countries like Vietnam due to the extremely complicated traffic patterns and lack of infrastructure. Firstly, motorcycles rather than passenger vehicles are by far the dominant vehicles for South East Asian countries. Moreover, road quality dramatically changes from one place to another. These factors lead to many traffic problems such as congestion and accidents. The purpose of this research is to implement a mobile system to monitor the traffic conditions which is applicable for deployment on Vietnamese roads. The system contains a set of sensors including a temperature sensor, humidity sensor, GPS receiver and two catadioptric cameras which are all mounted to a motorcycle. The two catadioptric cameras capture an overlapping 360° street view that observes the surrounding environment. The spherical camera images are flattened using an unconventional inverse mapping technique to preserve panoramic size without introducing blank pixel regions (as would be present for traditional Log-Polar to Cartesian mapping). All information captured from sensors and video will be used to identify hazards and to model the road users in Vietnam. This data is envisioned to facilitate studies of rider interactions to enhance driver awareness through education and road planning to improve road safety.

Parallel Random Access Memory in a shared memory architecture

Parallel algorithms can significantly speed up computing performance. However, parallel architecture often needs shared-memories for concurrent access. Conventionally, parallel memories are constructed as space-multiplexed memories with many memory chips connected in parallel. This architecture normally requires a large number of interconnects with potentially large routing delay and consumes massive area. This proposal develops a new memory component called Parallel Random Access Memory (P-RAM) with four identical parallel ports. This component is designed using VHDL hardware description language and emulated on Cyclone II FPGA. The P-RAM is not a conventional RAM memory since its four ports can be read and write concurrently. It can be used for many purposes such as shared memory for multiple processors in a parallel model. The design of the P-RAM component has been fully tested in both simulation and hardware integration with processors. Five simulation test cases were used to test all possible access cases of P-RAM and they all passed. The P-RAM is synthesized as combinations of logic elements (flip-flops and logic gates) instead of normal memory bits since it is a new component to the synthesis tool. lKB P-RAM take about 11,630 logic elements. The proposed P-RAM Parallel System has two instances (distinct copy) of the P-RAM component. One is used as shared instruction memory and the another is used as shared data memory. To demonstrate P-RAM operations, one port is used to observe data memory content and 3 CPUs are connected to the other ports of P-RAM component. Due to the FPGA chip resource limitation, the P-RAM instruction memory is built with only lKB size (32-bit data 8-bit address buses). The instruction code of the parallel algorithm is hard-coded in this memory by direct memory initialization. From this memory, the parallel algorithm of Finding the Maximum is run on all processors. The P-RAM data memory has 4-bit data and 4-bit address buses.

Magnetic Camera for visualizing Magnetic Fields of Home Appliances

Household appliances need to meet electromagnetic compatibility standards. We have developed a system to detect, observe and monitor magnetic field strength generated from electrical components and household appliances. The system comprises of an array of Hall Effect sensors, a video camera and a computer. Using the proposed system, magnetic field strength of tested device can be captured and displayed in a three-dimensional surface map. Several examples are demonstrated to capture and observe the magnetic field strength of tested devices.

Location-demanded data delivery over vehicular ad hoc networks

Vehicular ad hoc networks (VANET) have great potentials in modernizing transportation infrastructure. Deployment of data communications over such systems however is challenging due to node mobility. Unlike traditional networking scenarios, a user initiating a session for seeking traffic data (called receiver) is assumed to not know the identity associated with the counterpart. In reality, he or she instead likely issues data request with location description, rather than with identity description. In this sense, our study introduces a new notion of location-demanded session control and data delivery in a tenet of cross-layer design. We also let nodes communicate link quality to figure out the best route for a particular driver to look for an appropriate car who is able to return the traffic data that the receiver wishes. At the same time, we also implemented a route monitoring mechanism to assure an acceptable reliability of data delivery. Both simulations and experimental results demonstrate the feasibility and the soundness of the proposed strategy.

Implementation of fractal image encoding/decoding on DSP

Fractal image compression has been interested due to highly possible compression ratio and selectable quality variation. However, one of disadvantages in fractal image compression is that it takes long time for encoding. So far, there are several methods proposed to get the high speed of encoding such as Fishers, Hurtgens and Saupes, etc. In this paper, implementation of fractal image compression using Fishers and Hurtgens methods on DSP TMS320C5515 Stick kit is presented. Experimental results show that the Fishers method is faster than Hurtgens while the quality of decoded image (PSNR) is equivalently comparable in these methods.

Efficient implementation of a fractal color image compression on FPGA

Fractal Image Compression (FIC) method provides a color image compression solution with an extremely high compression ratio, however it requires relative large amount of operations to complete codification. In this paper, we have developed an efficient approach for a fractal image compression applied to a color image, which utilizes a fractal coding on RGB to YCrCb color transformation and suitable sampling modes, then implemented on FPGA board. The experimental results performed by Fishers method for a color image have verified the possibility to design a SoC for fast fractal coder/decoder of a color image.

Gradient Depth Map Based Ground Plane Detection for Mobile Robot Applications

In the field of navigation and guidance for mobile robots utilizing stereo visual imagery, the main problem to be solved is to detect the ground plane in acquired images by a stereo camera system mounted on the mobile device. This paper focuses on effective detection of ground based on graphical analysis of the gradient depth map evaluated on the input depth map within a given window. The detected ground planes is further divided into blocks and then classified into ground or non-ground regions for elimination of false detected ground planes followed by smoothing in refinement process. This proposed approach also has been shown to be effective in detection of obstacles appearing in the ground plane too while the mobile device is moving. In addition, the algorithm is simple, reliable, feasible, and may be efficiently exploited for implementation in an embedded hardware with limited resources for real-time applications.

Fast FPGA implementation of YUV-based fractal image compression

Fractal Image Compression (FIC) method provides a color image compression solution with an extremely high compression ratio and an relatively good PSNR. In this paper, we have developed an efficient approach for a fractal image compression applied to a color image, which utilizes a fractal coding on RGB to YUV color transformation at 4:1:1 sampling mode. The experimental results performed by Fishers method for a color image have verified the possibility to increase the compression ratio of FIC for color image while retaining an acceptable PSNR. Its purposed to design the low-bit-rate video encoding system by fractal coder/decoder of a color image.