Nian Zhang

Time series prediction with recurrent neural networks using a hybrid PSO-EA algorithm

To predict the 100 missing values from the time series consisting of 5000 data given for the IJCNN 2004 time series prediction competition, we applied an architecture which automates the design of recurrent neural networks using a new evolutionary learning algorithm. This new evolutionary learning algorithm is based on a hybrid of particle swarm optimization (PSO) and evolutionary algorithm (EA). By combining the searching abilities of these two global optimization methods, the evolution of individuals is no longer restricted to be in the same generation, and better performed individuals may produce offspring to replace those with poor performance. The novel algorithm is then applied to the recurrent neural network for the time series prediction. The experimental results show that our approach gives good performance in predicting the missing values from the time series.

Speeding up VLSI Layout Verification Using Fuzzy Attributed Graphs Approach

Technical and economic factors have caused the field of physical design automation to receive increasing attention and commercialization. The steady down-scaling of complementary metal oxide semiconductor (CMOS) device dimensions has been the main stimulus to the growth of microelectronics and computer-aided very large scale integration (VLSI) design. The more an Integrated Circuit (IC) is scaled, the higher its packing density becomes. For example, in 2006 Intels 65-nm process technology for high performance microprocessor has a reduced gate length of 35 nanometers. In their 70-Mbit SRAM chip, there are up to 0.5 billion transistors in a 110 mm2 chip size with 3.4 GHz clock speed. New technology generations come out every two years and provide an approximate 0.7 times transistor size reduction as predicted by Moores Law. For the ultimate scaled MOSFET beyond 2015 or so, the transistor gate length is projected to be 10 nm and below. The continually increasing size of chips, measured in either area or number of transistors, and the wasted investment involving fabricating and testing faulty circuits, make layout analysis an important part of physical design automation. Layout-versus-schematic (LVS) is one of three kinds of layout analysis tools. Subcircuit extraction is the key problem to be solved in LVS. In LVS, two factors are important. One is run time, the other is identification correctness. This has created a need for computational intelligence. Fuzzy attributed graph is not only widely used in the fields of image understanding and pattern recognition, it is also useful to the fuzzy graph matching problem. Since the subcircuit extraction problem is a special case of a general-interest problem known as subgraph isomorphism, fuzzy attributed graphs are first effectively applied to the subgraph isomorphism problem. Then we provide an efficient fuzzy attributed graph algorithm based on the solution to subgraph isomorphism for the subcircuit extraction problem. Similarity measurement makes a significant contribution to evaluate the equivalence of two circuit graphs. To evaluate its performance, we compare fuzzy attributed graph approach with the commercial software called SubGemini, and two of the fastest approaches called DECIDE and SubHDP. We are able to achieve up to 12 times faster performance than alternatives, without loss of accuracy

Investigation of Adaptive Filtering for Noisy ECG Signals

Studies shows that electrocardiogram (ECG) computer programs perform at least equally well as human observers in ECG measurement and coding, and can replace the cardiologist in epidemiological studies and clinical trials (J. A. Kors and G. V. Herpen, 2001). However, in order to also replace the cardiologist in clinical settings, such as for out-patients, better systems are required in order to reduce ambient noise while maintaining signal sensitivity. Therefore the objective of this work was to develop an adaptive filter to remove the contaminating signal in order to better obtain and interpret the electrocardiogram (ECG) data. To achieve reliability, the real-time computing systems must be fault-tolerant. This paper proposed a fault-tolerant adaptive filter for noise cancellation of ECG signals. Comparison of the performance and reliability of non-fault-tolerant and fault-tolerant adaptive filters are performed. Experimental results showed that the fault-tolerant adaptive filter not only successfully extract the ECG signals, but also is very reliable

The subcircuit extraction problem

The steady down scaling of CMOS device dimensions has been the main stimulus to the growth of microelectronics and computer aided very large scale integration (VLSI) design. But the more an integrated circuit (IC) is scaled, the higher its packing density becomes. The increasing size of chips, measured in either area or number of transistors, and the waste of the large capital investment involved in fabricating and testing circuits that do not work, make layout analysis and verification an important part of physical design automation. The most efficient way to overcome these difficulties is to identify a related collection of interconnected primitive devices in a circuit as a gate-level component. This is usually called the subcircuit extraction problem. The paper presents some background on subcircuit extraction. Subcircuit extraction is becoming a more critical issue with the increasing design sizes of very large scale integrated circuits (VLSICs). In the future, one of the most important tasks is to convert current stand-alone subcircuit extraction algorithms into economic benefits. We should make every effort to find those companies who would like to incorporate these algorithms into their VLSI layout verification software to speed up the process.

Application of collective robotic search using neural network based dual heuristic programming (DHP)

An important application of mobile robots is searching a region to locate the origin of a specific phenomenon. A variety of optimization algo-rithms can be employed to locate the target source, which has the maximum intensity of the distribution of some detected function. We propose a neural network based dual heuristic programming (DHP) algorithm to solve the collective robotic search problem. Experiments were carried out to investigate the effect of noise and the number of robots on the task performance, as well as the expenses. The experimental results were compared with those of stochastic optimization algorithm. It showed that the performance of the dual heuristic programming (DHP) is better than the stochastic optimization method.

A Switched-Resistor Approach to Hardware Implementation of Neural Networks

To overcome the shortcomings of fully analog and fully digital implementation of artificial neural networks (ANNs), we adopted mixed analog/digital technique. We proposed a switched-resistor (SR) element as a programmable synapse. The switched-resistor implementation of synapse captures both the advantages of analog implementation and the programmability of digital implementation. We also designed a CMOS analog neuron that performs a near-tanh nonlinearity function. We evaluated the performance of the neural networks using Pspice. The results showed that our approach can successfully implement the neural network, and exhibit a very high modularity