Nicholas Bonello

Reconfigurable rateless codes

We propose novel reconfigurable rateless codes, that are capable of not only varying the block length but also adaptively modify their encoding strategy by incrementally adjusting their degree distribution according to the prevalent channel conditions without the availability of the channel state information at the transmitter. In particular, we characterize a reconfigurable rateless code designed for the transmission of 9,500 information bits that achieves a performance, which is approximately 1 dB away from the discrete-input continuous-output memoryless channels (DCMC) capacity over a diverse range of channel signal-to-noise (SNR) ratios.

Low-Density Parity-Check Codes and Their Rateless Relatives

This survey guides the reader through the extensive open literature that is covering the family of low-density parity-check LDPC codes and their rateless relatives. In doing so, we will identify the most important milestones that have occurred since their conception until the current era and elucidate the related design problems and their respective solutions.

Construction of Regular Quasi-Cyclic Protograph LDPC Codes Based on Vandermonde Matrices

In this paper, we investigate the attainable performance of quasi-cyclic (QC) protograph low-density parity-check (LDPC) codes for transmission over both additive white Gaussian noise and uncorrelated Rayleigh channels. The presented codes are constructed using the Vandermonde matrix and thus have a girth of at least six in their corresponding Tanner graph. Furthermore, they also benefit from both low-complexity encoding and decoding, low memory requirements, as well as hardware-friendly implementations. Our simulation results demonstrate that the advantages offered by this family of QC protograph LDPC codes accrue with no compromise in the attainable bit error ratio (BER) and block error ratio (BLER) performances. In fact, it is also shown that despite their implementational benefits, the proposed codes exhibit slight BER/BLER gains when compared to some of their more complex counterparts of the same length.

Reconfigurable Rateless Codes

We propose novel reconfigurable rateless codes, that are capable of not only varying the block length but also adaptively modify their encoding strategy by incrementally adjusting their degree distribution according to the prevalent channel conditions without the availability of the channel state information at the transmitter. In particular, we characterize a reconfigurable rateless code designed for the transmission of 9,500 information bits that achieves a performance, which is approximately 1 dB away from the discrete-input continuous-output memoryless channels (DCMC) capacity over a diverse range of channel signal-to-noise (SNR) ratios.

Design of Low-Density Parity-Check Codes

This article provides an overview of the conflicting design tradeoffs of low-density parity-check (LDPC) codes and thus advocates a more holistic approach to their design for wireless channels. We reveal some of the intricate interdependencies of the LDPC code parameters and hence recommend designing codes that strike an attractive tradeoff concerning a number of desirable attributes, rather than simply designing codes that closely approach capacity but possess less-attractive hardware implementations.

Multilevel-Structured Low-Density Parity-Check Codes for AWGN and Rayleigh Channels

We propose a novel class of protograph low-density parity-check (LDPC) codes having a combinatorial rather than a random structure, which are termed multilevel-structured (MLS) LDPC codes. It is demonstrated that they posses a strikingly simple structure and, thus, benefit from reduced storage requirements, hardware-friendly implementations, and low-complexity encoding. Our simulation results provided for both additive white Gaussian noise (AWGN) and uncorrelated Rayleigh (UR) channels demonstrate that these advantages accrue without compromising the attainable bit error ratio (BER) and block error ratio (BLER) performance, when compared with their previously proposed more complex random-construction-based counterparts, as well as with other structured codes of the same length.

Channel Code-Division Multiple Access and Its Multilevel-Structured LDPC-Based Instantiation

In this paper, we introduce and outline the concept of channel code-division multiple access using a design example based on the recently proposed multilevel-structured (MLS) low-density parity-check (LDPC) codes. We succeeded in making the memory requirements of the multiuser transceiver to become practically independent of the total number of users supported by the system, as well as ascertain that each user benefits from the same level of protection. Finally, we will demonstrate that despite their beneficial compact structure, the proposed MLS LDPC codes do not suffer from any bit-error-ratio or block-error-ratio performance degradation, when compared to an otherwise identical benchmarker scheme using significantly more complex LDPC codes having pseudorandom parity-check matrices.

Generalized MIMO transmit preprocessing using pilot symbol assisted rateless codes

In this paper, we propose a generalized multipleinput multiple-output (MIMO) transmit preprocessing system, where both the channel coding and the linear MIMO transmit precoding components exploit the knowledge of the channel. This was achieved by exploiting the inherently flexible nature of a specific family of rateless codes that are capable of modifying their code-rate as well as their degree distribution based on the channel state information (CSI), in an attempt to adapt to the time-varying nature of the channel. Moreover, we also propose a novel technique, hereby referred to as pilot symbol assisted rateless (PSAR) coding, where a predetermined fraction of binary pilot symbols is interspersed with the channel-coded bits at the channel coding stage, instead of multiplexing the pilots with the data symbols at the modulation stage, as in classic pilot symbol assisted modulation (PSAM). We will subsequently demonstrate that the PSAR code-aided transmit preprocessing scheme succeeds in gleaning more beneficial knowledge from the inserted pilots, because the pilot bits are not only useful for estimating the channel at the receiver, but they are also beneficial in terms of significantly reducing the computational complexity of the rateless channel decoder. Our results suggest that more than a 30% reduction in the decoders computational complexity can be attained by the proposed system, when compared to a corresponding benchmarker scheme having the same pilot overhead but using the PSAM technique.

Channel Code Division Multiple Access and its Multilevel Structured LDPC Based Instantiation

In this paper, we introduce and outline the concept of channel code-division multiple access using a design example based on the recently proposed multilevel-structured (MLS) low-density parity-check (LDPC) codes. We succeeded in making the memory requirements of the multiuser transceiver to become practically independent of the total number of users supported by the system, as well as ascertain that each user benefits from the same level of protection. Finally, we will demonstrate that despite their beneficial compact structure, the proposed MLS LDPC codes do not suffer from any bit-error-ratio or block-error-ratio performance degradation, when compared to an otherwise identical benchmarker scheme using significantly more complex LDPC codes having pseudorandom parity-check matrices.

On the Design of Pilot Symbol Assisted Codes

We propose a novel technique, hereby referred to as pilot symbol assisted coding (PSAC), where a predetermined fraction of binary pilot symbols is interspersed with the channel-coded bits at the channel coding stage, instead of multiplexing the pilots with the data symbols at the modulation stage, as in classic pilot symbol assisted modulation (PSAM). We will subsequently demonstrate that the PSACaided scheme succeeds in gleaning more beneficial knowledge from the inserted pilots, because the pilot bits are not only useful for estimating the channel at the receiver, but they are also beneficial in terms of significantly reducing the computational complexity of the channel decoder. Our results suggest that in the specific application example considered the PSAC-aided scheme requires up to 45% fewer messagepassing updates per decoded bit than the corresponding channel coded PSAM benchmarker scheme.