Nick G. Eskandari

Architecture for an i/o processor that integrates a pci to pci bridge

Method and apparatus for pseudo-direct access to embedded memories of a micro-controller integrated circuit via the IEEE test access port

Trigger points for performance optimization in bus-to-bus bridges

Efficient bridge architecture for handling multiple write transactions simultaneously

Method and apparatus for asynchronous, bi-directional communication between first and second logic elements having a fixed priority arbitrator

Handling multiple delayed write transactions simultaneously through a bridge

Apparatus and method for pseudo-synchronous communication between clocks of different frequencies

Read latency across a bridge

Brücke zwischen zwei Bussen mit einem Puffer mit einer einstellbaren Mindestspeicherraummenge für ein Akzeptieren einer Schreibanforderung und Verfahren hierzu

Trigger points for performance optimization in bridges