Nicolas Delorme

Sigma-delta microsystems for readout and servo control

Several microsystem realizations are presented in this paper, which embed MEMs within a sigma-delta analog to digital (A/D) converter. A first category performs the readout and A/D conversion of capacitive sensors, while a second category, in addition to the readout and A/D conversion, provides advanced control techniques such as Proportional-Integral (PI) or Proportional-Integral-Derivative (PID) servo control to improve linearity and stability. A design methodology for this latter category is presented. For the readout-only microsystems category, the examples of pressure and acceleration readout are presented with SOI-based micromachined MEMs. Worst-case A/D conversion resolutions of 12 bits on 100Hz bandwidths are reported, with typical power consumptions for the A/D parts of around 500 μWatts. The pressure sensor microsystem includes full on-chip digital filtering and an RF powering and data transmission module for implanted applications. For the readout and servo control category, a porous silicon needle integrating a heating resistor and thermopiles is used to perform thermal conductivity measurements. Average A/D conversion resolution of 13 bits for 100Hz bandwidth is obtained and worst-case temperature regulation accuracy is 0.08 °C. Power consumption of the circuit remains around 500 μWatts. Detailed measurement results underline the valididy of the considered approaches for the implementation of high-compactness, high-resolution, improved-stability and low-power microsystems.

Influence of substrate type on interconnect peformance

Several interconnect configurations are used to discuss the influence of substrate configuration on interconnect performance. Electromagnetic simulations and high-frequency measurements are carried out on 2D and 3D structures built on both lightly-doped bulk and epitaxial heavily-doped bulk substrates.

Interconnection schemes for parasitics optimization

A set of four interconnection schemes is proposed to reduce parasitic ground and coupling capacitances and thus enhance technology performance. These strategies consist in: increasing the inter-metal dielectric thicknesses, using SiOF instead of SiO2, embedding the interconnects in a low-permittivity dielectric and switching to copper metallizations with constant line resistance. The effectiveness of these schemes is checked for the capacitances of simple 2D structures, for delay, crosstalk, and consumption in standard circuit routings, and for a 32 bits adder worst case delay and consumption.