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Dive into the research topics where Nicolas Heuck is active.

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Featured researches published by Nicolas Heuck.


international symposium on power semiconductor devices and ic's | 2015

Lifetime analysis of power modules with new packaging technologies

Nicolas Heuck; R. Bayerer; S. Krasel; F. Otto; R. Speckels; Karsten Guth

Several novel packaging technologies for power modules have been recently introduced to meet the future requirements of higher reliability and temperature stability. Using copper wire bonds for the top-side interconnect and silver sintered or diffusion soldered die attach layers led to a significant increase of lifetime. It was subsequently shown that the power cycling lifetime of modules without a baseplate is mainly limited by the substrate metallization, while modules employing a baseplate and a substrate-to-baseplate solder interconnect fail due to degradation within the solder layer. The investigations in this paper continue with the description and systematization of degradation effects in new interconnect technologies of power modules. As a result first lifetime models for modules with and without baseplate are provided. Thereby, accepted lifetime models for standard technologies are adopted to the degradation patterns of the new technologies.


Microelectronics Reliability | 2016

Reliability aspects of copper metallization and interconnect technology for power devices

Frank Hille; Roman Roth; Carsten Schäffer; Holger Schulze; Nicolas Heuck; Daniel Bolowski; Karsten Guth; Alexander Ciliox; Karina Rott; Frank Umbach; Martin Kerber

Abstract The introduction of thick copper metallization and topside interconnects as well as a superior die attach technology is improving the performance and reliability of IGBT power transistor technologies significantly. The much higher specific heat capacity and higher thermal conductivity increases the short circuit capability of IGBTs, which is especially important for inverters for drives applications. This opens the potential to further optimize the electrical performance of IGBTs for higher energy efficiency. The change in metallization requires the introduction of a reliable barrier against copper diffusion and copper silicide formation. This requires the development of an efficient test method and reliability assessment according to a robustness validation approach. In addition, the new metallization enables interconnects with copper bond wires, which yield, together with an improved die attach technology, a major improvement in the power cycling capability.


Materials Science Forum | 2016

History and Recent Developments of Packaging Technology for SiC Power Devices

Karl Otto Dohnke; Karsten Guth; Nicolas Heuck

Packaging plays an important role to allow the full potential of silicon carbide devices to be realised. The physical properties of silicon carbide will allow devices to operate with junction temperatures well above 200 °C, but today standard-packaged SiC products are limited to a maximum junction temperature of 175 °C. The limitation lies in the packaging, because a power device package is a complex structure consisting of many components of different materials and with correspondingly different thermal properties. As such, the assembly technologies define both the performance and lifetime of discrete packages and power modules. In this paper we give an insight of packaging technology for SiC devices from the beginning in the mid-1980s through to the state-of-the-art of today. In addition, new packaging technologies to enable power SiC devices to operate up to 200 °C are discussed.


european conference on power electronics and applications | 2015

Determination of parameters with high impact on fatigue of new Interconnect Technologies

Lukas Tinschert; Nicolas Heuck; Josef Lutz

The point of highest mechanical load in an interconnect layer, where crack propagation will start, depends strongly on geometry and material of the attached die as it was already indicated by the CIPS08 lifetime model for insulated models [1]. Therefore, simulations with the following varied geometry parameters were conducted: thickness, area and material of the die as well as thickness of the interconnect layer. Subsequently, the impact of each parameter on the fatigue of the interconnect layer will be discussed.


Archive | 2016

Method for Producing a Material-Bonding Connection between a Semiconductor Chip and a Metal Layer

Nicolas Heuck; Frederik Otto; Christian Steininger


Archive | 2012

Pre-Sintered Semiconductor Die Structure

Roland Speckels; Lars Böwer; Nicolas Heuck; Niels Oeschler


Archive | 2016

Method for Producing a Connecting Medium on an Assembly Partner, Method for Producing a Material-Fit Connection Between an Assembly Partner and a Metal Layer, and a System for Carrying out the Methods

Nicolas Heuck; Marco Marchitto; Roland Speckels


Archive | 2016

Verfahren zur Herstellung einer stoffschlüssigen Verbindung und Bestückungsautomat

Nicolas Heuck; Roland Speckels; Marco Marchitto


Archive | 2016

Method and device for generating layers with binder and forming material fitting connection

Marco Marchitto; Nicolas Heuck; Roland Speckels


Archive | 2015

METHOD FOR PRODUCING A DRIED PASTE LAYER and CONTINUOUS INSTALLATION

Alexander Ciliox; Christian Stahlhut; Nicolas Heuck

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