Nicole D. Kerness
Maxim Integrated
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Featured researches published by Nicole D. Kerness.
international electron devices meeting | 2013
Arkadii V. Samoilov; Khanh Tran; Nicole D. Kerness; Joy T. Jones; Peter McNally; Stanley Barnett; Tyler Parent; Joseph P. Ellul; Anu Srivastava; Kiyoko Ikeuchi; Tie Wang; Tiao Zhou
We illustrate capabilities of 3D integration for analog applications through both wafer-level and packaging technologies. Examples of wafer-level 3D integration include integrated capacitors and optical sensors. Integrated Si capacitors demonstrate the highest reported capacitor density of C=1 μF/mm2 (=1,000 fF/μm2) and the figure of merit (FOM) C*Vbd=11 C/m2 (Vbd is the breakdown voltage). Through-Si vias can be used to combine passive and active die into a single stack. Addition of optical layers to the Bipolar CMOS DMOS (BCD) process allows light detection in the visible and infrared range. 3D package-level integration is illustrated by embedding of multiple active and passive components in one package.
Archive | 2012
David Skurnik; Nevzat Akin Kestelli; Ilya K. Veygman; Anand Chamakura; Christopher F. Edwards; Nicole D. Kerness; Pirooz Parvarandeh; Sunny Kweisun Hsu
Archive | 2011
David Skurnik; Nevzat Akin Kestelli; Ilya K. Veygman; Anand Chamakura; Christopher F. Edwards; Nicole D. Kerness; Pirooz Parvarandeh; Sunny Kweisun Hsu
Archive | 2011
Prashanth Holenarsipur; Zhihai Wang; Nicole D. Kerness
Archive | 2014
Nicole D. Kerness; Arkadii V. Samoilov; Zhihai Wang; Joy T. Jones
Archive | 2013
Nicole D. Kerness; Joy T. Jones; Christopher F. Edwards; Arkadii V. Samoilov; Phillip J. Benzel; Richard I. Olsen; Peter R. Harper
Archive | 2011
Zhihai Wang; Nicole D. Kerness; Stanley Barnett
Archive | 2012
Nicole D. Kerness; Arkadii V. Samoilov; Zhihai Wang; Joy T. Jones
Archive | 2012
Nicole D. Kerness; Arkadii V. Samoilov; Zhihai Wang; Joy T. Jones
Archive | 2014
Nicole D. Kerness; Arkadii V. Samoilov; Zhihai Wang; Joy T. Jones