Nicolo Nizza

A Current-Mode, Dual Slope, Integrated Capacitance-to-Pulse Duration Converter

A capacitance-to-pulse duration converter, specifically designed for interfacing capacitive sensors, is presented. The operating principle is a double slope approach implemented using transconductor-based Miller integrators. The main strengths of the proposed circuit are: 1) intrinsically small sensitivity to temperature; 2) simplicity of trimming offset and gain to correct the sensor parameter spread; and 3) fast wake-up time. The circuit nonidealities are analyzed in order to identify the elements responsible for the residual temperature sensitivity and jitter on the pulse duration. The effectiveness of the method is demonstrated by measurements performed on a prototype, designed and fabricated using the 0.35 mum, 3.3 V Bipolar-CMOS-DMOS process BCD6 of STMicroelectronics.

A Low-Power Interface for Capacitive Sensors With PWM Output and Intrinsic Low Pass Characteristic

A compact, low power interface for capacitive sensors, is described. The output signal is a pulse width modulated (PWM) signal, where the pulse duration is linearly proportional to the sensor differential capacitance. The original conversion approach consists in stimulating the sensor capacitor with a triangular-like voltage waveform in order to obtain a square-like current waveform, which is subsequently demodulated and integrated over a clock period. The charge obtained in this way is then converted into the output pulse duration by an approach that includes an intrinsic tunable low pass function. The main non idealities are thoroughly investigated in order to provide useful design indications and evaluate the actual potentialities of the proposed circuit. The theoretical predictions are compared with experimental results obtained with a prototype, designed and fabricated using 0.32 μm CMOS devices from the BCD6s process of STMicroelectroncs. The prototype occupies a total area of 1025× 515 mm2 and is marked by a power consuption of 84 μW. The input capacitance range is 0-256 fF, with a resolution of 0.8 fF and a temperature sensitivity of 300 ppm/°C.

A low-power capacitance to pulse width converter for MEMS interfacing

A compact converter from capacitance to pulse width, suitable for interfacing integrated capacitive sensors is described. The circuit has been designed and fabricated using 0.32 mum/ 3.3 V CMOS devices from the BCD6s process of STMicroelectroncs and occupies an area of 1025 times 515 mum2. Measurements performed on the test chip showed an excellent linearity, a temperature drift of 300 ppm/degC, and power consumption as low as 84 muW for continuous operation.

A Fully Integrated Single-Ended 1.5–15-Hz Low-Pass Filter With Linear Tuning Law

A second-order, single-ended, fully integrated low- pass filter with cut-off frequency tunable in the range 1.5-15 Hz is presented. The filter is based on a recently proposed CMOS transconductor topology, combining Gm values of the order of a few nS with large input ranges and suitability to single-ended filter architectures. The circuit has been designed and fabricated using 3.3-V 0.35-mum CMOS devices from the STMicroelectronics Bipolar-CMOS-DMOS process BCD6. The tested prototype occupies an area of 960 x 350 mum2 and requires a supply current ranging from 50 to 500 muLambda, depending on tuning. Total harmonic distortion lower than 1% has been measured in a wide tuning range for 1-V peak-to-peak input signal amplitude. The effect of temperature on the tuning law in the interval 0-80degC is shown. A dynamic range in excess of 60 dB over the whole tuning range has been estimated from distortion and noise measurements.

CMOS Transconductors With Nearly Constant Input Ranges Over Wide Tuning Intervals

Three different bias strategies aimed to reduce the effect of tuning on either the differential input range or the common-mode range of triode-region CMOS transconductors are presented. The method is applied to an original transconductor topology that is optimized to produce ultralow Gm values. A prototype circuit, which was designed with the 0.35-mum bipolar-CMOS-DMOS (BCD6) process of STMicroelectronics, is presented. The effectiveness and limitations of the method are characterized by means of electrical simulations

A four quadrant analog multiplier based on a novel CMOS linear current divider

An analog, Gilbert-like CMOS multiplier, based on a novel linear current divider, is described. The divider uses a cascade of two differential pairs to produce a linear dependence between the tail current and the two output currents. A numerical algorithm has been implemented to find the optimum sizing of the active devices in order to compensate for the deviation from the ideal MOSFET square law. The results of low frequency measurements performed on a prototype, designed with CMOS devices from the STMicroelectronic process BCD6s, are shown.

A four quadrant CMOS analog multiplier based on the non ideal MOSFET I–V characteristics

This paper concerns an analog CMOS multiplier based on a novel approach to compensate for non idealities of the MOSFET square law approximation. A numerical algorithm has been implemented to find the optimum sizing of the active devices, starting from the process characteristics. The effectiveness of the proposed configuration has been demonstrated by means of electrical simulations performed on a prototype cell, designed using 0.32 mum - 3.3 V CMOS devices from the STMicroelectronic process BCD6s.

A low power capacitance to pulse width converter for integrated sensors

An interface circuit for integrated capacitive sensors with pulse width modulated output is presented. The circuit is based on an original architecture implementing offset and low frequency noise cancellation by means of chopper modulation. Electrical simulations, performed on a prototype designed using 0.32 mum/ 3.3 V CMOS devices, showed that a sensitivity to temperature lower than 10 ppm/degC with a power consumption of 66 muW can be obtained with this approach.

A non linear ADC for sensor linearization

A successive approximation ADC with nonlinear characteristic is presented as an effective method for sensor linearization. Drastic simplification of the ADC structure was obtained by implementing a piece wise linear approximation of the required non linear curve. The design and simulated performance of an 8-bit prototype, applied to the linearization of a real flow sensor, are presented.

A fully integrated very low frequency single-ended Gm-C filter based on a novel transconductor

A second order fully integrated low pass filter with cut-off frequency variable in the range 1.5-15 Hz is presented. The filter is based on a recently proposed CMOS transconductor topology combining G m values of the order of a few nS with large input ranges and suitability to single-ended filter architectures. The performances are validated by simulations performed on a prototype designed with the 0.35 mum BCD6 process of STMicroelectronics. In particular, a dynamic range of 70 dB and power dissipation of 60 muW have been obtained with a corner frequency of 1.5 Hz