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Dive into the research topics where Nikita Ambasana is active.

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Featured researches published by Nikita Ambasana.


electrical performance of electronic packaging | 2014

Application of artificial neural networks for eye-height/width prediction from s-parameters

Nikita Ambasana; Dipanjan Gope; Bhyrav M. Mutnury; Gowri Anand

Signal speeds of high speed serial data links double almost every generation and with increasing speeds, simulation and modeling challenges are getting more complex. The present popular and widely accepted metric for simulating a high speed link from signal integrity (SI) perspective is Bit Error Rate (BER) testing. SI engineers look at eye-height and eye-width to determine the quality of an interface for a given set of design parameters. In order to perform BER simulations, time domain simulations need to be performed over billions of bits for serial links using statistical approaches and these simulations are time, processing power and memory intensive. Design of Experiments (DoE) is typically used to decrease the number of time-domain simulations needed to cover the design space, however it is sometimes in-accurate as compared to full-factorial design sweeps. End to end channel simulation in frequency domain is much faster and less resource intensive. In this paper, a DoE based set of channel parameters are simulated in both time-domain and frequency-domain to train a multi-layer perceptron (MLP) type of artificial neural network (ANN) to predict eye-height from frequency domain metrics like return loss (RL) and insertion loss (IL). This results in a significant speed-up towards a more accurate all corner study as compared to DoE based analysis.


IEEE Transactions on Components, Packaging and Manufacturing Technology | 2016

Eye Height/Width Prediction From

Nikita Ambasana; Gowri Anand; Bhyrav M. Mutnury; Dipanjan Gope

Design space exploration and sensitivity analysis for electrical performance of high-speed serial links is a critical and challenging task for a robust, cost-efficient, and signal-integrity-compliant channel design. The generation of time-domain (TD) metrics like eye height and eye width at higher bit error rates requires longer bit sequences in TD circuit simulation, which is compute time intensive. Intelligent techniques to identify smaller design sets that cover the design space optimally may provide incorrect sensitivity analysis. This paper explores learning-based modeling techniques that rapidly map relevant frequency-domain metrics like differential insertion loss and total cross talk, in the presence of equalization, to TD metrics like eye height and eye width, thus facilitating a full-factorial design space sweep. Numerical results performed with multilayer-perceptron-based artificial neural network as well as least-squares support vector machine (LS-SVM) on Serial ATA 3.0 and Peripheral Component Interconnect Express Gen3 channels generate an average error of less than 2%.


electrical design of advanced packaging and systems symposium | 2014

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Nikita Ambasana; Dipanjan Gope; Bhyrav M. Mutnury; Gowri Anand

Validation of high-speed interface performance in a given design space from a Signal Integrity (SI) perspective requires Bit Error Rate (BER) computation. Eye Height (EH) and Eye Width (EW) are used to determine the quality of an interface for a given set of design parameters and frequency of operation. EH, EW and BER estimation requires Time Domain (TD) simulation of complex channel models over billions of bits, which is a time, compute power and memory intensive process. Statistical and optimization techniques such as Design of Experiments (DoE) based on generation of design sets that span the design space optimally exist today. However, it has been shown that DoE based simulations might result in in-accurate sensitivity analysis for highly nonlinear design spaces. Also, the size of a DoE set scales exponentially with the number of design variables. It has been shown in [5] that TD metrics EH and EW, in absence of cross-talk, can be mapped from FD metrics like Return Loss (RL) and Insertion Loss (IL) using Artificial Neural Networks (ANN). The training of the ANNs requires DoE for the existing method. In this paper, an alternative technique to DoE, for generating a training set for ANN is presented, which remains constant over several number of design variables, and scales only in the number of FD metrics used to map to TD metrics and the number of samples in FD. Simulations for SATA 3.0 channel topology with and without cross-talk in TD are presented to quantify the accuracy of the said approach.


IEEE Transactions on Components, Packaging and Manufacturing Technology | 2017

-Parameters Using Learning-Based Models

Nikita Ambasana; Gowri Anand; Dipanjan Gope; Bhyrav M. Mutnury

Design and analysis of high-speed SerDes channels primarily deal with ensuring signal integrity (SI) for desired electrical performance. SI is predominantly judged by time domain (TD) metrics: bit error rate (BER), eye-height (EH), and eye-width (EW). With increasing bit rates and stringent BER criteria, TD simulations are becoming compute-time-intensive. A full-factorial, cost-effective design space exploration for SI is made possible by learning-based mapping of frequency-domain S-parameter data to EH/EW. A major challenge in this mapping procedure is the identification of relevant S-parameter data, such as return loss, insertion loss, crosstalks, and the frequency points at which they are sampled. This paper outlines a methodology to identify the critical S-parameters at specific frequency points using information theory-based definition of data relevance using a fast correlation-based filter solution for feature selection. This technique is applied for identifying relevant features for generating artificial neural network-based prediction models of EH/EW within 2.5% accuracy for channels with high data rates and complex topologies.


electrical performance of electronic packaging | 2016

Eye-height/width prediction from S-Parameters using bounded size training set for ANN

Nikita Ambasana; Bibhu Prasad Nayak; Dipanjan Gope

Accurate Power Distribution Network (PDN) design is crucial for Signal/Power Integrity (SI/PI) and Electromagnetic Interference (EMI) compliance. Achieving target power-ground (PG) noise levels for low power complex PDNs requires several design and analysis cycles. Although several classes of analysis tools, 2.5D and 3D, are commercially available, the presence of design tools are limited e.g. parametric design space exploration using multiple forward analysis. In this work, a frequency domain mesh-based sensitivity formulation for DC and AC impedance of PDNs is proposed. The two main objectives include: (i) highlighting layout regions to the designer for maximum impact in achieving target specifications and (ii) predicting the results of a design variant with mesh-based sensitivity information from the base-design. The time required for updating the results for the design variant is negligible compared to a complete re-simulation.


electrical design of advanced packaging and systems symposium | 2016

S-Parameter and Frequency Identification Method for ANN-Based Eye-Height/Width Prediction

Nikita Ambasana; Dipanjan Gope; Bhyrav M. Mutnury; Gowri Anand

In the field of High Speed SerDes (HSS) channel analysis and design, the most widely accepted metrics for gauging signal integrity are Time Domain (TD) metrics: Bit Error Rate (BER), Eye-Height (EH) and Eye-Width (EW). With increasing bit-rates, TD simulations are getting compute-time intensive especially as the BER criterion is getting lower. Learning based mapping of Frequency Domain (FD) S-Parameter data to EH/EW in TD provides a fast alternative solution for thorough design-space exploration. A key challenge in this mapping procedure is the identification of the optimal frequency points in the S-Parameter data that are used for training the learning network. This paper outlines a methodology to identify the minimal set of critical frequency points using a Fast Correlation Based Feature (FCBF) selection algorithm. This technique is applied for prediction of EH/EW for a PCIe Gen 3 interface and the prediction accuracy is quantified.


electrical performance of electronic packaging | 2015

Mesh-based impedance sensitivity formulation for DC/AC Power Integrity design and diagnosis

Nikita Ambasana; Bhyrav M. Mutnury; Dipanjan Gope

IRIS is a consolidated platform to analyse bulk S-Parameter data, perform operations like termination/renormalization of port impedances, conversion from single-ended to mixed mode, evaluate complex equations in S-Parameters, plug-in, view and record violation of envelopes as defined by SATA, SAS, PCIe & USB spec sheets. It also implements a novel machine-learning based methodology [1] to efficiently bridge Frequency Domain (FD) and Time Domain (TD) by predicting Eye-Height (EH) and Eye-Widths (EW) from S-Parameters.


electrical performance of electronic packaging | 2013

Automated frequency selection for machine-learning based EH/EW prediction from S-Parameters

Nikita Ambasana; Dipanjan Gope; Arun Chandrasekhar

Package-board co-design plays a crucial role in determining the performance of high-speed systems. Although there exist several commercial solutions for electromagnetic analysis and verification, lack of Computer Aided Design (CAD) tools for SI aware design and synthesis lead to longer design cycles and non-optimal package-board interconnect geometries. In this work, the functional similarities between package-board design and radio-frequency (RF) imaging are explored. Consequently, qualitative methods common to the imaging community, like Tikhonov Regularization (TR) and Landweber method are applied to solve multi-objective, multi-variable package design problems. In addition, a new hierarchical iterative piecewise linear algorithm is developed as a wrapper over LBP for an efficient solution in the design space.


ieee workshop on signal and power integrity | 2017

Intelligent rapid investigation of S-parameters (IRIS)

Nikita Ambasana; Dipanjan Gope


Archive | 2016

Application of qualitative imaging methods to electrical performance-aware package board design

Bhyrav M. Mutnury; Gowri Anand; Nikita Ambasana

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Dipanjan Gope

Indian Institute of Science

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Bibhu Prasad Nayak

Indian Institute of Science

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