Nikola Celanovic

A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters

This paper explores the fundamental limitations of neutral-point voltage balancing problem for different loading conditions of three level voltage source inverters. A new model in DQ coordinate frame utilizing current switching functions is developed, as a means to investigate theoretical limitations and lend more intuitive insight into the problem. The low frequency ripple of the neutral point caused by certain loading conditions is observed and quantified.

Permanent Magnet Synchronous Generator Cascade for Wind Turbine Application

This paper proposes an energy conversion system for a wind turbine comprising a grid connected permanent magnet synchronous generator and a 20% rated series converter located in its star point. It models the complete system and focuses on the series converter control whose primary function is the active damping of the generator. In addition, this paper addresses the topic of the dc bus voltage control and the dc capacitance sizing of the series converter. Finally, it validates the performance of the proposed system by means of system simulation.

HIL Evaluation of Power Flow Control Strategies for Energy Storage Connected to Smart Grid Under Unbalanced Conditions

This paper proposes two power flow control algorithms for a grid-connected voltage source converter used as part of the energy storage for a smart grid under unbalanced voltage conditions. Both algorithms are improvements of the dual vector current control algorithm (DVCC). The first proposed algorithm, DVCC_CL, optimizes the method of limiting phase currents for the duration of voltage unbalance. The second proposed algorithm, DVCC_HB, provides high bandwidth control of active and reactive power. Which of the two proposed algorithms is the better choice depends on the grid code requirements and the constraints imposed by the particular energy storage system which the inverter connects to the grid. The operation of both algorithms was verified within the framework of an ultralow-latency hardware-in-the-loop emulator, which makes accurate analysis of converter behavior safe and easy for any grid conditions.

Ultralow-Latency Hardware-in-the-Loop Platform for Rapid Validation of Power Electronics Designs

This paper introduces a unified approach to the validation of power-electronics (PE) control hardware, firmware, and software designs. It is based on a scalable application-specific ultralow-latency (ULL) digital processor core. The proposed ULL processor core simulates PE converters and systems comprising multiple power converters with a fixed 1-μs simulation time step and latency, regardless of the size of the system. Owing to its ULL, the proposed platform enables the fully automatic testing and validation of the complete PE design comprising component safe-operating-area validation, system protection, firmware, and software implementation as well as overall system performance optimization.

A new control architecture for future distributed power electronics systems

This paper proposes a novel open-architecture approach to the design of digital controller hardware for power electronics systems. The paper discusses the benefits of such an approach and compares it to the more conventional centralized controller approach. Prototypes of the three key open-architecture functional blocks: high-speed serial communication link, hardware manager and application manager were built in order to test their performance on a representative three-phase 100 kVA converter. Experimental results verify the feasibility of the proposed approach.

The feedforward method of controlling three-level diode clamped converters with small DC-link capacitors

This paper introduces a control method, which enables the distortion-free operation of a three-level converter in the presence of significant neutral point voltage ripple. Application of this control method allows a trade-off between the voltage capacity of the switching devices and the size of the DC-link capacitors.

Development of High-Reliability EV and HEV IM Propulsion Drive With Ultra-Low Latency HIL Environment

This paper proposes an improved and robust method of minimizing the error in propulsion-drive line-currents that are reconstructed from a single dc-link current measurement. The proposed algorithm extends and then shortens the relevant phase pulse-widths in order to provide optimal sampling of the dc-link currents in two consecutive pulsewidth modulation (PWM) periods. The proposed PWM pattern control enables an improved sampling method which cancels offset jitter-like waveform errors present in all three reconstructed line-currents, which is due to a specific combination of nonsimultaneously sampled dc-link current and line-current PWM ripple. The improvement in induction motor drive accuracy using a single current-sensor and no shaft sensor (as proposed in this paper), over that of conventional methods, is shown. Thanks to an ultra-low latency hardware-in-the loop (HIL) emulator, the proposed algorithm, its implementation on a DSP processor, code optimization and “laboratory” testing were all merged into one development step. In order to perform final tests of the proposed current-reconstruction algorithm and to verify the usefulness of the developed HIL platform by means of comparison, experimental results obtained on a real hardware setup are provided.

Control design of three-level voltage source inverter for SMES power conditioning system

This paper describes the control design of the power processing system for superconductive magnetic energy storage (SMES). The proposed SMES power-processing system consists of series connection of a three-level voltage source inverter and a three-level chopper. The control design enables stable high-bandwidth control of power transfer to and from the SMES coil. The issues of series connection of power converters are discussed. Theoretical analysis of the controller design and experimental results are presented.

Ultralow Latency HIL Platform for Rapid Development of Complex Power Electronics Systems

Prototyping and verification of complex power electronics (PE) systems and control algorithms is a laborious and time-consuming process. Even when a low-power hardware model is assembled, it enables only a limited insight into the large number of operating points; changes in system parameters regularly demand hardware modifications and always there is the risk of hardware damage. The ultralow-latency Hardware-In-the-Loop (HIL) platform proposed in this paper combines the flexibility, accuracy, and ease of use of state-of-the-art-simulation packages, with the response speed of small power-hardware models. In this way, PE systems-optimization, code-development, and laboratory-testing can be combined into one step, which dramatically accelerates the pace of product prototyping. Low-power hardware-models also suffer from nonscalability, because some parameters such as electrical machine inertia cannot be properly scaled. However, HIL enables control prototyping that covers all operational conditions. In order to demonstrate HIL-based rapid development, the verification of an active damping algorithm for a permanent magnet synchronous generator (PMSG) cascade is performed. Two goals are set in this paper: to verify the developed HIL platform by means of comparison with a low-power hardware setup and then to emulate the real, high-power system in order to test the active damping algorithm.

Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems

The smart grid concept is a good example of a complex cyber-physical system (CPS) that exhibits intricate interplay between control, sensing, and communication infrastructure on one side, and power processing and actuation on the other side. The more extensive use of computation, sensing, and communication, tightly coupled with power processing, calls for a fundamental reassessment of some of the prevailing paradigms in the real-time control and communication abstractions. Today these abstractions are mostly thought of as embedded systems, and the overall framework needs to be reformed in order to fully realize the potential of the emerging field of cyber-physical systems. This paper details the design and application of a new ultrahigh speed real-time emulation platform for Hardware-in-the-Loop (HiL) testing and design of high-power power electronics systems. Our real-time hardware emulation for HiL systems is based on a reconfigurable, heterogeneous, multicore processor architecture that emulates power electronics, and includes a circuit compiler that translates graphic system models into processor executable machine code. We present the hardware architecture, and describe the process of power electronic circuit compilation. This approach yields real-time execution on the order of 1µs simulation time step (including input/output latency) for a broad class of power electronics converters. To the best of our knowledge, no current academic or industrial HiL system has such a fast emulation response time. We present HiL experimental results for three representative systems: a variable speed induction motor drive, a utility grid connected photovoltaic converter system, and a hybrid electric vehicle motor drive.