Nilanka T. Rajapaksha

Multiplier-free DCT approximations for RF multi-beam digital aperture-array space imaging and directional sensing

Multi-beamforming is an important requirement for broadband space imaging applications based on dense aperture arrays (AAs). Usually, the discrete Fourier transform is the transform of choice for AA electromagnetic imaging. Here, the discrete cosine transform (DCT) is proposed as an alternative, enabling the use of emerging fast algorithms that offer greatly reduced complexity in digital arithmetic circuits. We propose two novel high-speed digital architectures for recently proposed fast algorithms (Bouguezel, Ahmad and Swamy 2008 Electron. Lett. 44 1249?50) (BAS-2008) and (Cintra and Bayer 2011 IEEE Signal Process. Lett. 18 579?82) (CB-2011) that provide good approximations to the DCT at zero multiplicative complexity. Further, we propose a novel DCT approximation having zero multiplicative complexity that is shown to be better for multi-beamforming AAs when compared to BAS-2008 and CB-2011. The far-field array pattern of ideal DCT, BAS-2008, CB-2011 and proposed approximation are investigated with error analysis. Extensive hardware realizations, implementation details and performance metrics are provided for synchronous field programmable gate array (FPGA) technology from Xilinx. The resource consumption and speed metrics of BAS-2008, CB-2011 and the proposed approximation are investigated as functions of system word size. The 8-bit versions are mapped to emerging asynchronous FPGAs leading to significantly increased real-time throughput with clock rates at up to 925.6?MHz implying the fastest DCT approximations using reconfigurable logic devices in the literature.

Low-Power VLSI Architectures for DCT\/DWT: Precision vs Approximation for HD Video, Biomedical, and Smart Antenna Applications

The DCT and the DWT are used in a number of emerging DSP applications, such as, HD video compression, biomedical imaging, and smart antenna beamformers for wireless communications and radar. Of late, there has been much interest on fast algorithms for the computation of the above transforms using multiplier-free approximations because they result in low power and low complexity systems. Approximate methods rely on the trade-off of accuracy for lower power and/or circuit complexity/chip-area. This paper provides a detailed review of VLSI architectures and CAS implementations for both DCT/DWTs, which can be designed either for higher-accuracy or for low-power consumption. This article covers both recent theoretical advancements on discrete transforms in addition to an overview of existing VLSI architectures. The paper also discusses error free VLSI architectures that provides high accuracy systems and approximate architectures that offer high computational gain making them highly attractive for real-world applications that are subject to constraints in both chip-area as well as power. The methods discussed in the paper can be used in the design of emerging low-power digital systems having lowest complexity at the cost of a loss in accuracy?the optimal trade-off of computational accuracy for lowest possible complexity and power. A complete synopsis of available techniques, algorithms and FPGA/VLSI realizations are discussed in the paper.

2D space---time wave-digital multi-fan filter banks for signals consisting of multiple plane waves

Two dimensional space–time fan filters may be used for the highly-selective enhancement of spatio-temporal plane-waves on the basis of their directions of arrival. Unlike uniform bandwidth beam filters, ideal fan filters transmit passband signals over a range of directions of arrival that is independent of their 1D temporal spectrum. In this work, closed-form 2D wave-digital filter design equations and corresponding hardware architectures are proposed for realizing M independent fan-shaped passbands having independently steerable directionality and selectivity. A design method based on LCR ladder networks is proposed and implemented using a 2D time-multiplexed raster-scanned architecture that is suitable for low frequency applications such as audio, multimedia, seismic and ultrasonic beamforming. The architectures are designed, simulated, physically realized and tested on FPGA-based prototypes. Examples of 2D IIR M-fan filterbanks with FPGA implementations, together with measured results from on-chip hardware verifications, show the successful design and hardware realization. The filterbanks and hardware architectures are shown to be suitable for real-time sensor-array beamforming applications using custom VLSI circuits.

A Single-Channel Architecture for Algebraic Integer-Based 8

An area efficient row-parallel architecture is proposed for the real-time implementation of bivariate algebraic integer (AI) encoded 2-D discrete cosine transform (DCT) for image and video processing. The proposed architecture computes 8 × 8 2-D DCT transform based on the Arai DCT algorithm. An improved fast algorithm for AI-based 1-D DCT computation is proposed along with a single channel 2-D DCT architecture. The design improves on the four-channel AI DCT architecture that was published recently by reducing the number of integer channels to one and the number of eight-point 1-D DCT cores from five down to two. The architecture offers exact computation of 8 × 8 blocks of the 2-D DCT coefficients up to the FRS, which converts the coefficients from the AI representation to fixed-point format using the method of expansion factors. Prototype circuits corresponding to FRS blocks based on two expansion factors are realized, tested, and verified on FPGA-chip, using a Xilinx Virtex-6 XC6VLX240T device. Post place-and-route results show a 20% reduction in terms of area compared to the 2-D DCT architecture requiring five 1-D AI cores. The area-time and area-time2 complexity metrics are also reduced by 23% and 22% respectively for designs with eight-bit input word length. The digital realizations are simulated up to place and route for ASICs using 45 nm CMOS standard cells. The maximum estimated clock rate is 951 MHz for the CMOS realizations indicating 7.608·109 pixels/s and a 8 × 8 block rate of 118.875 MHz.

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Transformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on asynchronous quasi delay-insensitive logic, using Achronix SPD60 field programmable gate array (FPGA), which leads to lower complexity, higher speed of operation, and insensitivity to process-voltagetemperature variations. Performance of AI DCT with HEVC is measured in terms of the accuracy of the transform coefficients and the overall rate-distortion (R-D) characteristics, using HM 7.1 reference software. Results indicate a 31% improvement over the integer DCT in the number of transformcoefficients having error within 1%. The performance of the 65 nmasynchronous hardware in terms of speed of operation is investigated and compared with the 65 nm synchronous Xilinx FPGA. Considering word lengths of 5 and 6 bits, a speed increase of 230% and 199% is observed, respectively. These results indicate that AI DCT can be potentially utilized in HEVC for applications demanding high accuracy as well as high throughput. However, novel quantization schemes are required to allow the accuracy improvements obtained.

8 2-D DCT Computation

A new class of continuous-time (CT) two-dimensional (2D) filters based on available 2D IIR wave digital filters (WDFs) is proposed. This class of CT filters is free of the aliasing and switching power dissipation of discrete-time versions and also free of the quantization noise caused by digital underflow. Importantly, the transfer functions do not undergo warping in the temporal-frequency domain due to the bilinear transformation. The method essentially approximates each ideal CT delay element of the 2D IIR WDFs with an analog all-pass block. VLSI circuit implementations of the proposed method are described where inverter-based CMOS circuit that implements the required all-pass transfer function is simulated using 90 nm CMOS BSIM4 models in Cadence.

Asynchronous realization of algebraic integer-based 2D DCT using achronix speedster SPD60 FPGA

Two-dimensional (2D) beam filters find applications in highly-selective directional enhancement of spatio-temporal (ST) plane-waves (PWs). A 2D raster-scanned (RS) wave-digital filter (WDF) hardware architecture, using a uniform linear array (ULA) of sensors, based on a 2D LR-ladder prototype network is proposed for obtaining M independently-steerable broadband beams having adjustable selectivity. FPGA-based prototypes for 2,3 beams supporting upto 32 broadband sensors are as well as measured results, FPGA resource consumptions, and maximum speeds at various fixed-point precisions, are provided. On-chip verification of the M-beam 2D IIR beam WDF architecture leads to multi-beamforming in applications such as directional audio, multimedia, seismic, and ultrasonic signal processing.

A new class of spatially-discrete time-continuous 2D IIR filters based on wave-digital-filter theory

A 2-D massively parallel, high throughput, systolic array for a spatio-temporal wave-digital filter (WDF) architecture is proposed. RF receive mode aperture beam personalities are achieved using 2-D fan filters with dynamically steerable passband directions and fan angles. The wave-digital realization results in low sensitivity of the far-field beam to errors in filter coefficients due to fixed-point effects in the digital arithmetic hardware. A fixed-point design of the systolic-array architecture that eliminates overflow errors is described. The architecture is implemented in FPGA-prototype form and tested using MATLAB Simulink with Xilinx EDA tools. The verified digital design is ported to CMOS standard-cell technology to obtain the area and power costs as well as the operational frequency. The 45 nm CMOS synthesis, placement, and routing show overflow free maximum frequency of operation of 131.02 MHz for 1-passband fan filter and an estimated power consumption of 450.30 mW at DC supply voltage 1.1 V indicating potential applications in the VHF range.

Raster-scanned wave-digital filter architectures for multi-beam 2D IIR broadband beamforming

This paper investigates the potential of emerging asynchronous quasi delay insensitive (a-QDI) logic devices for the realization of high-speed low-power 2D infinite impulse response digital beam filters. Recently proposed raster-scanned hardware architectures based on direct-form I and wave-digital realization are extended to clock-free asynchronous logic using state-of-the-art asynchronous field programmable gate arrays from Achronix Semiconductor. For the specific class of 2D IIR beam filters based on raster-scanned hardware, it is shown using extensive experimental work that direct-form I architectures greatly benefit from the adoption of a-QDI logic over standard clocked (synchronous) digital circuits while wave-digital filters show no difference in performance. To the authors knowledge, the proposed 2D IIR hardware circuits are currently the only available realization of 2D IIR filters in the literature based on the new clock-free a-QDI paradigm.

Systolic array architecture for steerable multibeam VHF wave-digital RF apertures

The discrete cosine transform (DCT) is a widely-used and important signal processing tool employed in a plethora of applications. Typical fast algorithms for nearly-exact computation of DCT require floating point arithmetic, are multiplier intensive, and accumulate round-off errors. Recently proposed fast algorithm arithmetic cosine transform (ACT) calculates the DCT exactly using only additions and integer constant multiplications, with very low area complexity, for null mean input sequences. The ACT can also be computed non-exactly for any input sequence, with low area complexity and low power consumption, utilizing the novel architecture described. However, as a trade-off, the ACT algorithm requires 10 non-uniformly sampled data points to calculate the eight-point DCT. This requirement can easily be satisfied for applications dealing with spatial signals such as image sensors and biomedical sensor arrays, by placing sensor elements in a non-uniform grid. In this work, a hardware architecture for the computation of the null mean ACT is proposed, followed by a novel architectures that extend the ACT for non-null mean signals. All circuits are physically implemented and tested using the Xilinx XC6VLX240T FPGA device and synthesized for 45 nm TSMC standard-cell library for performance assessment.