Nils-Peter Harder

Charge carrier lifetime degradation in Cz silicon through the formation of a boron-rich layer during BBr3 diffusion processes

Boron diffusion is commonly associated with the formation of an undesirable boron-rich layer (BRL), which is often made responsible for degradation of the carrier lifetime in the bulk. We investigate the phenomenology of the BRL formation, which results from BBr3 boron diffusion processes, and its impact on sheet resistance and bulk lifetime. Our measurements show that boron silicate glass (BSG) and BRL thicknesses vary between 50 and 600 nm and 0 and 80 nm respectively within the two-dimensional wafer surface of one sample for one diffusion process. Both thicknesses strongly depend on the gas composition during composition and deposition time. Further results show that BRL formation is favored by high concentrations of BBr3 vapor and of oxygen during B2O3 deposition. Also, high drive-in temperatures promote the growth of the BRL. We find that a BRL of more than 10 nm thickness causes a degradation of the carrier lifetime in the bulk of the silicon wafer. In particular, we show that this bulk lifetime degradation occurs during the cool-down ramp after the diffusion process. We show that carrier lifetime degradation can be avoided either by limiting the process temperature to 850 °C and thus preventing BRL formation or through reconverting the BRL by a drive-in step in oxidizing atmosphere at 920 °C.

Impact of surface topography and laser pulse duration for laser ablation of solar cell front side passivating SiNx layers

Local contact openings in SiNx layers that passivate the front side of solar cells offer an attractive alternative to the current standard “fire-through” screen printing process for front grid fabrication. Additionally, this technology can be used for enabling a selective emitter. In the present paper, we investigate laser ablation of SiNx layers on planar and textured silicon surfaces for various laser wavelengths and pulse durations in the nanosecond (ns) to femtosecond (fs) range. We characterize the dark J-V characteristics of diodes with laser contact openings in the SiNx layer passivating the emitter. Our results show that on alkaline textured surfaces the ablation by a ns laser produces less damage than by an ultrashort pulse laser. The dark currents of alkaline textured diodes treated with picosecond (ps) or fs lasers are one order of magnitude higher than those of ns laser treated diodes. High ideality factors furthermore indicate crystal damage in the ∼500 nm deep space charge region of the diod...

Surface passivation of n-type Czochralski silicon substrates by thermal-SiO2/plasma-enhanced chemical vapor deposition SiN stacks

The surface passivation properties of thermal-SiO2/plasma-enhanced chemical vapor deposition SiN stacks on 2.5 Ω cm n-type Czochralski silicon substrates have been investigated. By annealing these stacks in air we achieve surface recombination velocities (SRV) lower than 2.4 cm/s for thin SiO2 layers. We find a clear correlation between the thickness of the oxide layers and the annealing duration. We also show that the absolute passivation quality of the SiO2/SiN stacks correlates to the SiO2 thickness. We find that the SRV increases with increasing oxide thickness. We also present data of the surface passivation of these SiO2/SiN stacks after storage in the dark for several weeks.

A Simple Model Describing the Symmetric

We present an analytical model for the current transport in polycrystalline (poly)Si/interfacial oxide/monocrystalline ( c)-Si base junctions, which consistently describes the symmetrical behavior of an n+ poly-Si emitter/ p c-Si base and p+ poly-Si emitter/ n c-Si base configuration. Our model is focused on a regime within which the current transport is possibly dominated by a flow through oxide pinholes rather than by tunneling. For an emitter region assumed to form underneath the interfacial oxide by diffusion of dopants from the poly-Si into the c-Si, we calculate the minority charge carrier distribution and the resistance implied for majority charge carriers. With reasonable parameters, our model simultaneously reproduces the experimentally observed low emitter saturation current densities and low junction resistances values. Our model provides a plausible explanation for the high current gain observed in p-n-p and n-p-n bipolar transistors featuring a poly-Si emitter. In principle, the obtained correlation between recombination current and series resistance is analogous to the situation in a base region of a solar cell with local rear contacts. Thus, a poly-Si/ c-Si junction can be explained within the framework of a classical p-n junction picture for a passivated, locally contacted emitter.

I\hbox{--}V

In the ALBA-II project, Q-Cells SE, Bitterfeld-Wolfen, Germany, and the Institute for Solar Energy Research Hamelin, Emmerthal, Germany, are developing high-efficiency emitter-wrap-through (EWT) solar cells on n-type silicon wafers. N-type silicon grown by the Czochralski (Cz) method forms the basis of this high-efficiency solar cell development as it offers high bulk carrier lifetimes. The EWT device structure allows us to employ a simplified process sequence compared with interdigitated back-contact back-junction solar cells. High open-circuit voltages of our solar cells are achieved by different passivation layers for base and emitter surfaces and picosecond laser ablated contact openings. An optimization of the resistances along the current paths in base and emitter leads to an improvement in fill factor (FF) over former EWT solar cells. Together with the inherently high current densities of EWT solar cells, we achieve on our small-area (4-cm2, designated area without busbars) cells a short-circuit current density JSC of 40.4 mA/cm2, an open-circuit voltage VOC of 661 mV, FFs well above 80%, and, thus, cell efficiencies of up to 21.6%.

Characteristics of

Currently, the emitter-wrap-through (EWT) design of Si solar cells is being intensively investigated as a potential candidate for cheap, low-quality Si materials. So far, experimentally achieved energy conversion efficiencies have stayed unexpectedly far below the expectations of common device theory. Therefore, we analyze fabricated EWT cells in detail and refine device theory to account for the limiting loss mechanisms present only in EWT cells. By means of rigorous three-dimensional numerical device modeling, we show that the fill factor (FF) is significantly reduced, primarily due to a effect we call the via-resistance induced recombination enhancement effect. The FF is only secondarily reduced by the resistive losses in the vias where the emitter is wrapped through the cell. This implies that lowering the base resistivity will improve cell efficiency more effectively than lowering the resistance in the vias. Our simulations predict that the EWT design with a nonpassivated rear emitter and a homogeneo...

\hbox{p}

Local contacts through dielectric layers are an important prerequisite for the production of very high efficiency SiO2-or SiNx-passivated silicon solar cells. We use laser ablation as a contactless process for local removal of dielectric layers. This contactless process is suitable for processing very thin wafers without cell breakage. Carrier lifetime measurements indicate that our laser ablation process produces no or only negligible damage to the silicon crystal. Open-circuit voltages of solar cells which were locally contacted through laser ablated SiNx underline the finding that the crystal damage is negligible. High fill factors and low series resistances of 0.6 Ohmcm2 reveal the successful local opening of the passivating dielectric layer. These properties qualify local laser ablation of passivating dielectric layers for the production of high-efficiency solar cells. In addition, the contactless nature of laser ablation makes this technique attractive for processing very thin silicon wafers

Polycrystalline Si/

In this work, we investigate the applicability of counterdoping by ion implantation for the formation of pn-junctions for high efficiency interdigitated back contacted silicon solar cells. Counterdoping offers the possibility of creating the emitter with a blanket implantation and the back surface field with a masked implantation, leading to an elegant process without the need of precise alignment between the two implantation steps. We analyze I-V curves of diodes after implantation and high temperature annealing and compare the results with numerical simulations. Despite the presence of highly doped boron and phosphorous regions in contact to each other, neither trap assisted tunneling nor dominant recombination in the space-charge region is observed in forward direction. This result reflects the excellent removal of implant damage during the co-annealing step. In reverse direction, a sharp breakdown due to band-to-band-tunneling is observed at -8 V. Since it occurs very homogenously across the whole wafer and no local hot spots are observed, no implications for module reliability are implied.

\hbox{n}

We present an experimental method to quantify the series resistance R_a-Si/ITO through the a-Si:H layers and the a-Si:H/ITO interface on test structures. In order to optimize R_a-Si/ITO, we apply different a-Si:H and ITO deposition parameters. We find the best value for R_(p)-a-Si/ITO of 0.42 Ω·cm² for an ITO double layer with a 10-nm-thin starting layer that provides good contact resistance and an additional 90-nm top layer that provides good conductivity. For R_(n)-a-Si/ITO, we reach values below 0.1 Ω·cm². We present an analysis of the series resistance and shading losses of our 100-cm² bifacial screen-printed a-Si:H/cSi heterojunction solar cells, which show an open-circuit voltage of V_oc = 733 mV, demonstrating the excellent level of interface passivation. The efficiency of 20.2% is limited by a low short-circuit current density of 37.1 mA/cm² and fill factor of 76%.

Monocrystalline Si, and

Increasing the area of interdigitated back-contact (IBC) solar cells featuring a busbar contact geometry requires the use of longer fingers. The finger resistance will, thus, be increased if the thickness of the metallization is kept constant. In order to maintain a thin metallization, it is beneficial to increase the number of busbars per contact. However, using more than one busbar for each polarity implies an asymmetric contact geometry. As a consequence, under operation, the busbars of the same polarity carry different currents. Due to voltage drops over unavoidable electrical resistances, this may lead to significant potential differences between these busbars. Since current–voltage characteristics are usually measured using separate sense contacts for the voltage measurement, the position and number of these contacts may considerably affect the shape of the resulting current–voltage characteristic and, thus, the fill factor. By means of simulations with the circuit simulator LTSpice, we show that a permanent contacting with soldered tabs allows for a correct determination of the fill factor. A chuck used for temporary contacting should feature at least one sense contact per busbar and pin contacting resistances below 30 mΩ in order to keep the fill factor error below 0.5% absolute.