Nirmal R. Saxena

Method and apparatus for a single history register based branch predictor in a superscalar microprocessor

Method and apparatus to efficiently store error codes

Reconfigurable data packet header processor

Predicting for all branch instructions in a bunch based on history register updated once for all of any taken branches in a bunch

Method and apparatus for detecting duplicate entries in a look-up table

Reconfigurable control processor for multi-protocol resilient packet ring processor

Branch prediction based on correlation between sets of bunches of branch instructions

Method, system and apparatus for efficiently generating binary numbers for testing storage devices

METHOD AND APPARATUS FOR IMPROVED BRANCH PREDICTION ACCURACY IN A SUPERSCALER MICROPROCESSOR

ERROR DETECTION AND CORRECTION METHOD