Nivo Rovedo

A new asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer n-MOSFET design for reliability and performance

A novel asymmetrical n-MOSFET device structure has been developed which is suitable, in terms of reliability and performance, for scaling down to the sub-quarter-micron level, without reduction of the supply voltage below 3.5 V. In this structure (HS-GOLD), large-tilt implantation is used to form the gate-overlapped lightly doped drain (GOLD) region at the drain electrode only. A halo (punch-through stopper) is used at the source, but not at the drain. Superior hot-carrier reliability and high punch-through resistance are obtained using this device structure. A reliability-limited supply voltage at 4.2 V is obtained for HS-GOLD n-MOSFETs with effective channel lengths as short as 0.25 mu m. High punch-through resistance is achieved without extreme scaling of S-D (source-drain) junctions and gate oxide (120 AA). The threshold roll-off characteristics suggest that this n-MOSFET structure can be designed with about 0.3 mu m shorter channel length (L/sub eff/=0.15 mu m) while maintaining the 3.5-V supply voltage. Reliable operation of 0.15- mu m n-MOSFETs at 3.5-V supply voltage using the proposed device structure is demonstrated by 2D simulation. >

A half micron MOSFET using double implanted LDD

Double-implanted LDD, which consists of self-aligned p pockets below the n regions in LDD, is introduced to improve both breakdown and short channel effects. Its fabrication and experimental results are presented. The device optimized for a 0.5µm channel and 3.5V supply is discussed.

The effects of fluorine on parametrics and reliability in a 0.18-/spl mu/m 3.5/6.8 nm dual gate oxide CMOS technology

Fluorine was introduced into the gate oxide by implantation at various doses into the gate polysilicon. After complete processing, the fluorine remaining in the system was characterized by secondary ion mass spectroscopy (SIMS) and then correlated to a number of important technological device parameters. The threshold voltages of thin (3.5 nm) and thick (6.8 nm) field-effect transistors (FETs) were measured, and an increase in interface trap density with increasing fluorine content was identified. An increase in oxide thickness and improvement in hot-carrier immunity were observed. Little change to oxide dielectric integrity was noted, but the negative bias threshold instability (NBTI) shift was improved with the introduction of fluorine. These data indicate that benefits may be obtained by introducing fluorine into the p-type FET (PFET), but that the increase in interface traps makes fluorine in the n-type FET (NFET) less attractive from a technological perspective. These data are in agreement with a previously proposed mechanism whereby fluorine removes hydrogen-related sites from the oxide.

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described in this paper. Gate length and dielectric scaling, along with optimized strain engineering, enable high performance devices, which are amongst the best reported to date. Short channel effect control down to 35 nm is demonstrated. Both NMOS and PMOS performance are improved through careful optimization of stress effects from both trench isolation and contact etch stop nitride film. Furthermore, analysis of the channel mobility and current enhancement is used to gain understanding of the stress mechanisms, and hence layout design practice should be optimized for performance.

Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs

The physical mechanism responsible for negative bias temperature instability (NBTI), which is basic to the minimization of this degradation mode, is investigated, and an analytical model is developed accordingly. Experiments with 1.7 nm to 3.3 nm gate dielectrics fabricated by different processes demonstrate the capability of the proposed model.

Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy

Current drive enhancement is demonstrated in sub-40 nm NFETs with strained silicon carbon (Si:C) source and drain using a novel solid-phase epitaxy (SPE) technique for the first time. The very simple process uses no recess etch or epi deposition steps, adds minimal process cost, and can be easily integrated into a standard CMOS process. With a record high 1.65 at% substitutional C concentration in source and drain, 615 MPa uniaxial tensile stress was introduced in the channel, leading to a 35% improvement in electron mobility and 6% and 15% current drive increase in sub-40 and 200 nm channel length devices respectively.

Scalability and biasing strategy for CMOS with active well bias

We analyze the scalability of the two well bias strategies: reverse bias to reduce standby power, and forward bias to improve the speed or to reduce active power. We then present the device design space that includes well bias as an integral part of the design variables following the SIA Roadmap specifications. We show that proper well biases are needed for bulk CMOS just to continue to meet the SIA Roadmap requirements for performance and standby current. The scalabilities for forward bias and reverse bias are different. The advantage of reverse bias is diminishing with scaling due to low initial V/sub t/ values, short-channel effects, and band-to-band tunneling. The advantage of the forward body bias is preserved better with scaling due to high initial V/sub t/ values as well as smaller depletion width, and increases with V/sub t/ nonscaling. The forward bias approach is not effective in speed improvement for ultra-high performance applications with high V/sub dd/ overdrive and low V/sub t/ to start with, but is effective in active power reduction at a fixed speed target.

Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices

We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770muA/mum at Ioff = 100nA/mum with VDD = 1V. Competitive nFET performance was maintained. Parasitics such as silicide and junction characteristics were not degraded

High performance cmos bulk technology using direct silicon bond (dsb) mixed crystal orientation substrates

High performance 65-nm technology (Lpoly=45nm, EOT=1.2nm) bulk CMOS has been demonstrated for the first time on mixed orientation substrates formed by using direct silicon bonded (DSB) wafers and a solid phase epitaxy (SPE) process. The pFET performance is improved by 35% due to hole mobility enhancement on (110) surfaces as compared to (100) surfaces. nFETs on SPE-converted (100) surfaces exhibit the same performance as those on (100) controls. Ring oscillators fabricated using DSB with SPE show improvements of more than 20% compared with control CMOS on (100) surfaces

Design of high performance PFETs with strained si channel and laser anneal

The effects of the integration of two major PFET performance enhancers, embedded SiGe (e-SiGe) junctions and compressively stressed nitride liner (CSL) have been examined systematically. The additive effects of e-SiGe and CSL have been demonstrated, enabling high performance PFET (drive current of 640 muA/mum at 50 nA/mum off state current at 1V) with only modest Ge incorporation (~20 at. %) in S/D. And for the first time, we have demonstrated that by integrating e-SiGe and laser anneal (LA), defect-free e-SiGe can be fabricated, and the benefits of both techniques can be retained. Our study of geometric effects also reveals that e-SiGe can be extended to 45 nm technology and beyond