Nobuhiko Sugino

Code optimization method utilizing memory addressing operation and its application to DSP compiler

Methods to derive an efficient memory access pattern for DSPs of which memory is accessed only by address registers (ARs) are discussed. Variables in a program and AR operations are modeled by an access graph. A novel memory allocation method, which removes cycles and forks in a given access graph, and decides an efficient address location of variables in memory space, is proposed. In order to utilize multiple ARs, methods to assign variables into ARs are investigated. The method based on min-cut algorithm is superior to the method based on the simulated annealing technique. The proposed methods are applied to the compiler for DSP56000 and generated codes for several examples are very much improved.

Computational ordering of adaptive digital networks under pipeline constraints and its application to DSP compilers

A novel computational ordering of adaptive digital networks for a digital signal processor (DSP) with multiple stages of pipeline is proposed. Optimization techniques for conditional branches are also introduced. By use of these methods, the number of overhead codes related to pipeline hazards and delayed branches is reduced.

Effective ad hoc social networking on OLSR MANET using similarity of interest approach

Recently, social networking over MANETs has attracted the attention of research community, due to its flexibility, cost saving and infrastructure-less architecture. However, various problems namely, to efficiently find nodes of similar interest and network partition, exist in such environment. For enabling ad hoc social networking in an intermittent network scenario, Delay Tolerant Network (DTN) emerges as one of the solution. This paper proposes a novel algorithm allowing users to find friends of similar interest both in their neighborhood and in entire network by using DTN on OLSR MANET. We investigate and compare the similarity of users interest using four similarity metrics: Cosine Similarity, Jaccard, Correlation and Dice Coefficient. We simulate the algorithms assuming that users change their interest at fixed and random time (normal and uniform distribution). The simulations results show that Cosine Similarity provides the highest number of similar interest matching. In addition, by implementing the proposed algorithm on DTN with the normal distributed users interest-changing time, the success ratio of finding matches increases significantly.

Improved code optimization method utilizing memory addressing operation and its application to DSP compiler

Improved methods to derive an efficient memory access pattern for DSPs, of which memory is accessed only by address registers (ARs), are discussed. In this article, variables in a program and AR operations are modeled by a novel access graph. The number of possible AR operations between two memory accesses are used as one of the weights for every edge. After removal of appropriate cycles and forks in a given graph with taking weights on edges, an efficient memory allocation is decided. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for /spl mu/PD77230, and resultant memory allocations for several examples are very much improved.

Adaptive Channel Access Mechanism for Real Time Traffic over IEEE 802.11e Wi-Fi Network

The deployment of Wi-Fi network has been growing rapidly due to its ease of implementation and affordability in prize. The increase in number of users and applications results in increment of multimedia traffic in Wi-Fi networks. There are lots of performance issues in Wi-Fi network with respect to Quality of Services (QoS), especially with voice and video applications. In this paper we propose the adaptive channel access mechanism to improve the performance of real time traffic under high traffic environment. The proposed adaptive channel access mechanism improves the performance of voice and video traffic by 15% to 20% in terms of packet delay and throughput under high traffic load environment.

Memory allocation methods for a DSP with indirect addressing modes and their application to compilers

For a DSP with address registers (ARs), which point memory addresses to be accessed, memory allocation methods to reduce overhead codes in accesses are discussed. In the existing heuristic method, variables in a program and AR operations are modeled by a graph, and modification of the graph according to a cost function leads to an efficient address location. In this paper, this method is iteratively applied and the most efficient address locations in sense of a cost function (sub-optimal locations) are derived. This iterative method is applied to the compiler for /spl mu/PD77230 (NEC), and computational time for deriving efficient memory locations is proved to be relatively shorter than that of the exhaustive search method for the global optimal address locations. Second, a new cost function for the graph linearization algorithm which considers locality of addresses in memory accesses is proposed. This cost function is utilized in the compiler and an efficient address location, which is comparable to the optimal/sub-optimal allocations, is derived in a very short computational period.

DSP memory allocation method for indirect addressing with wide range update operation by multiple registers

A novel method to derive an efficient memory access pattern for digital signal processors (DSPs), of which memory is accessed only by address registers (ARs), is proposed. In this paper, the AR update scheme is extended such that address can be efficiently modified within /spl plusmn/k in addition to conventional /spl plusmn/1 updates. The method formulates program variables and AR modifications by a graph, and extracts a maximum chained clique graph with k+1 vertices, which is accessed only by AR update operations within /spl plusmn/k, so that the estimated number of overhead codes is minimized. In order to utilize multiple ARs, a method to assign memory accesses into ARs is also studied. The proposed methods are applied to a DSP compiler, and memory allocations derived for several examples are compared with memory allocations by other methods.

Code optimization method for DSPs with multiple memory addressing registers and its application to compilers

A novel method to derive an efficient memory access pattern for a digital signal processor (DSP) of which memory is accessed only by address registers (ARs), is discussed. In such a DSP, some AR operations are performed very efficiently, and program codes with less overhead in memory accesses are derived by utilizing such AR operations as much as possible. By utilizing multiple ARs, further reduction in overheads in codes is possible. In the existing code optimization method methods, variables in a program are assigned into respective ARs, and then the location of the variables in memory space is decided. Those methods, however, strictly limit the address range accessed by each AR. In this article, a novel AR assignment method is performed for memory access sequence of which the memory location is already settled. The memory re-allocation method, which swaps the location of variables related with overheads, is also studied. The proposed methods are applied to the compiler for /spl mu/PD77230, and resultant codes for several examples are comparable to the existing methods.

A Cross-layer design approach in OLSR MANET using BER and weighted Connectivity Index

Usually, Optimized Link State Routing (OLSR) protocol, a proactive routing protocols in MANET, is not aware of Quality of Service (QoS). Recently, the new approach called cross layer design has been proposed to improve the performance of wireless network, especially in MANET. In this work, we propose a heuristic approach based on cross layer design scheme to enhance performance of OLSR by using Bit Error Rate (BER) derived from physical layer together with a network layer parameter called weighted Connectivity Index (CI) which is a combination between the link connectivity and capacity. In our proposed heuristic algorithm, the approach is to find the optimized path in terms of highest weighted CI and lowest BER in order to improve the performance of Multipoint Relays (MPR) selection algorithm and route computation. The performances of the proposed scheme are investigated by simulation using Throughput, Packet Delivery Ratio, Average End-to-End Delay and Control Overhead as evaluation metrics. We compare the simulation results of our proposed scheme with the standard OLSR protocol and OLSR with only weighted CI approach. According to the simulation results, it is obvious that our proposed scheme illustrates the improvement of OLSR on the afore-mentioned evaluation metrics over the standard OLSR protocol and OLSR with weighted CI.

CT/US Image Registration Using LS-SVM

Image registration is the process of mapping coordinates between one image and another, in order to achieve a correct correspondence. Medical image is one of research field that have benefited from image registration technique. Registration of pre-operative image dataset and intra-operative images owns great value of efficiency to analyze the differences between the images, especially, in the field of radiation surgery and neurosurgery. For this purpose, we studied the appropriate mapping between CT and ultrasound image, in order to observe the possibility to perform the image guide surgery. We applied Least Square Support Vector Machine which is a tool based on a statistical learning theory, as the key technique in mapping the different data, to minimize the mapping time in the registration process. The experimental results show that the LS-SVM based image registration method yields high accuracy with simplicity of practical application.