Nobukazu Doi

Digital Video Recording Techniques Using 1/2 Inch Metal Particle Tape

During the past ten years, rapid progress has been made in development of recording techniques for home use VTR. Nevertheless, a limit has now been reaches to improvement in such functional areas as SN ratio, resolution, and dubbing. It is now expected that digital recording techniques will be introduced into the video field in the future to assure even further development.

Partial-response decoding of rate 1/2 modulation codes for digital storage

In digital storage systems, receivers for rate 1/2 modulation codes are usually oversampled by a factor of two with respect to the data stream that they attempt to reconstruct. It is shown that oversampling may be avoided by using partial-response techniques to detect, instead of the encoded binary signal, a decimated ternary one, from which the original data can be recovered by means of a simple decoder. A method is described to find all such decoders for a given rate 1/2 code. Examples treated are FM, MFM, Miller-squared,

Adaptive DCT coding for home digital VTR

The authors investigate fixed adaptive discrete cosine transform (FADCT) coding for use in digital VTRs (video tape recorders). The image is divided into 8*8-pixel subblocks, and a two-dimensional DCT is performed on each of them. The quantization scheme is adapted to input image data, thereby increasing coding efficiency. The scheme is designed, however, to keep the output data rate fixed. Computer simulation showed that FADCT coding improves the SNR (signal/noise ratio) from 1 dB to 3 dB as compared to nonadaptive DCT coding, and a high-quality image with SNR over 40 dB can be obtained at 3 bits/pixel. Reallocations of the extra bits from the higher to the lower AC energy subblocks allow the application of adaptive coding to the digital VTR, with a high tolerance for channel errors.<<ETX>>

DS/CDMA prototype system transmitting low bit-rate voice and high bit-rate ISDN signals

The DS/CDMA prototype system described can transmit low bit-rate voice and high bit-rate ISDN signals in the ISM band. The robust error correction scheme uses interleaving, convolutional coding, and Reed-Solomon coding; it ensures high quality voice and ISDN signals. The relationship between the SNR and and the number of quantizing bits output by the ADC of SS signals has been evaluated, and it has been shown that an ADC with few-bits has minimal SNR degradation in CDMA systems. The received and despread signals are quasi-coherently detected in the forward link by referring to the phase of the pilot signal, whereas in the reverse link, non-coherent or differential detection is used. The proposed DS/CDMA prototype system has shown to achieve good performance in various experiments using a wireless TV-phone, developed as a potential ISDN application.<<ETX>>

Spread spectrum slot reservation multiple access

A new method of data transmission is proposed for mobile communications. It is similar to the traditional split channel reservation multiple access (SRMA): a mobile user (MU) reserves transmission slots from a base station (BS) and then transmits according to the BS scheduling. However, in the proposed method a number of MUs can transmit concurrently using the direct sequence spread spectrum (DS-SS) technique. The DS-SS technique is also used at the reservation stage where a multiple-slotted-ALOHA (m-S-ALOHA) technique allows multiple users to simultaneously reserve service. Theoretical and simulation results show significant increases in throughput efficiency for the proposed method compared with the traditional SRMA technique.

A proposal of new architecture for W-CDMA baseband LSI

In this paper, a new architecture called Multi-Engine is proposed for W-CDMA baseband LSI. Multi-Engine architecture processes multiple channels at the base station by time-multiplexing. By processing at high speed such as 200 MHz, more than 10 channels can be accommodated in 1 LSI. The engines are controlled by software programs, allowing more flexibility to correspond to several modes of IMT-2000 standard. We have evaluated its effect by designing Multi-Engine on FPGA, and completed its software for the W-CDMA scheme.

Code reassignment scheme on CDMA smart antenna systems

This paper proposed code reassignment scheme on CDMA smart antenna systems. The proposed scheme suppresses multi-channel access interference (MAI) caused by the shortage of an orthogonal spreading code in a sector. Computer simulation shows an 18% capacity gain and 3 dB reduction of Tx power on the down link.

A study on the accuracy of a CDMA-based location system

Recently, positioning of the handset from which the calls occur has been required for public safety. For emergency services, USA wireless carriers have been obligated to provide a position location at the handset and the services are called Enhanced 911 (E911). We have developed a IS-95-based location system which uses forward link trilation (FLT) techniques. Performance evaluations in various environments through simulations are often required and the evaluation technique is the key issue for efficient development of such location systems. In this paper, the simulation model proposed here is verified with a field trial. The simulation results and the trial results show good agreement. The results show that the proposed scheme could give the ability to evaluate the performance of the location system. Then, this paper shows simulation results of the location accuracy in typical environments with actual geometric configuration of the handset and the base stations. The results show that the location system achieves positioning accuracy which satisfies the E911 requirements.

Experiments on automatic equalizer without increased noise for digital recording systems.

ディジタル記録システムで発生する符号間干渉 (ISI) を雑音の増加なく除去できる等化器を開発した.本等化器は下記2つの手法で構成している. (1) 識別再生信号を用いてISIのコピーを作成し, これを元の信号から差し引くことでISIを除去する.この後, 再度識別再生し, データを復元する, (2) 復元データ中の符号誤りの位置を上記2種の識別再生信号をモジュロ2加算すすことで検出する.つぎに, この誤り位置に対応する符号の信頼度を再生信号の振幅値の大小に基づき判定し, 誤りを訂正する.実験とシミュレーションにより, 本等化器は再生信号の符号誤り率が10-2の場合に, これを約2桁改善できることを示した.同時に, 自動等化のためのディジタル, アナログいずれの回路構成でも使用できる簡易タップ係数収束アルゴリズムを提案し, その妥当性を解析した.これを用いて, 46Mb/sの高速動作可能なディジタル自動等化器を構成し, 良好な収束特性が得られることを示した.