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ieee computer society international conference | 1990

Fujitsu VP2000 series

Nobuo Uchida; M. Hirai; M. Yoshida; K. Hotta

A description is given of the Fujitsu VP2000 series, a new-generation supercomputer supporting full compatibility with previous VP and VP-E series, and with much higher performance. The VP2000 series has a performance range of between 0.5 and 4 GFLOPS. It features a dual scalar processor architecture, expanded main storage, system storage, and connectivity to UNIX environments. The series offers a wide range of vector performance, with the most powerful model being eight times faster than the entry-level model. Whereas Model 10 has a uniprocessor architecture, Model 20 is a dual scalar processor system in which two scalar units can share one vector unit. The VP2000 series has a total of eight models that are field upgradable. The new features in architecture, LSI technology, and software are discussed.<<ETX>>


International Journal of High Speed Computing | 1991

FUJITSU VP2000 SERIES SUPERCOMPUTERS

Nobuo Uchida

Fujitsu VP2000 series Supercomputer is a pipeline supercomputer series developed by Fujitsu. The peak performance of this series ranges from 375 MFLOPS of the VP2100/10S to 5 GFLOPS of the VP2600/10. Operations are mainly performed by using a pipeline which is called “Universal Pipeline”. This pipeline provides a capability of one of the following operations such as a multiplication, an addition, a multiplication-addition or a logic operation at one time. In addition, in case that two pipelines are used, they can perform such operations concurrently. The VP2200, the VP2400 and the VP2600 have two pipelines and both pipelines are used for multiplication-addition concurrently to attain the peak performance. FORTRAN77 EX/VP, which is developed to utilize this hardware, makes it possible to schedule these two pipelines effectively. Using the VP2600/10, the performances of LINPACK problem for a matrix of order 100 and for a matrix of order 1000 are 249 MFLOPS and 4009 MFLOPS respectively.


Archive | 1991

Multiprocessor control system

Nobuo Uchida; Yasuhiro Kuroda; Shoji Nakatani


Archive | 1994

Data processing system including different throughput access sources accessing main storage in same direction

Kenji Korekata; Nobuo Uchida


Archive | 1988

Main storage access priority control system that checks bus conflict condition and logical storage busy condition at different clock cycles

Nobuo Uchida; Yuji Oinaga; Mikio Itoh


Archive | 2006

System clock distributing apparatus and system clock distributing method

Nobuo Uchida


Archive | 1989

Data processing system including different throughput access sources

Kenji Fujitsu Dai Nakahara-Ryo Korekata; Nobuo Uchida


Archive | 1989

Multiprocessor memory access control system

Nobuo Uchida; Yasuhiro Kuroda; Shoji Nakatani


Archive | 1988

Access priority control system for main storage for computer

Nobuo Uchida; Yuji Oinaga; Mikio Itoh


Archive | 1989

Datenverarbeitungssystem mit Zugriffsquellen von verschiedenem Durchsatz.

Kenji Korekata; Nobuo Uchida

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