Norhuzaimin Julai

Performance of CMOS Schmitt Trigger

This paper presents the effect of load capacitance and source voltage on performance of proposed Schmitt trigger circuit. The proposed circuit was designed based on Conventional Schmitt Trigger by manipulating the arrangement of transistors and the width-length ratio. All simulation results have been carried out based on Microwind software on three different designs in term of propagation delay, Energy-delay Product and hystheresis. From the result, the proposed full swing CMOS Schmitt Trigger was able to operate as low voltage (0.8 V-1.5 V).

Wireless communication techniques, the right path to Smart Grid distribution Systems: A review

The quality and reliability of electric power supply are the key indicators for the comfort of a society. Hence, to serve customers with high quality electricity, the Supervisory Control and Data Acquisition (SCADA) system is being used in the distribution system (DS) for power monitoring and control. The SCADA is feed with operation data like current and voltage via Feeder_Remote Terminal_Units (FRTUs). The FRTUs are capable of triggering actions to detach the portion of DS experiencing an unusual condition. Nevertheless, the existing grids do not operate at their optimal capacity due to the usage of one way data communication installations. Thus, to optimize the operation of the legacy power distribution grids, the innovation of the state-of-the-art communication techniques play a vital role-leading to the creation of smart grid Systems. This paper reviews the development of wireless communication technologies envisioned as full-duplex information exchange medium in the on-going development of Smart Grid Systems.

Impact of poly field plate dimension towards LDMOS performance

Rapid increasing demand towards high voltage MOSFETs device integrated in low voltage CMOS analog and digital circuits for automobile and power management application has driven the development of 0.18 um high voltage lateral diffused MOSFET (LDMOS) which capable to have 80 V breakdown voltage. During designing this high voltage LDMOS, it is observed that the device performance is very dependent towards the device geometry particularly poly overlap length on STI. Thus, in this paper, the effects of poly overlap length on STI plate for high voltage LDNMOS have been studied extensively during the off-state condition.

The Analysis of Soft Error in C-Elements

With the rapid growth of communications via the Internet, the need for an effective firewall system which has not badly affect the overall network performances has been increased. In this paper, a Field Programmable Gate Array (FPGA) -based firewall system with high performance has been implemented using Network FPGA (NetFPGA) with Xilinx Kintex-7 XC7K325T FPGA. Based on NetFPGA reference router project, a NetFPGA-based firewall system was implemented. The hardware module performs rule matching operation using content addressable memory (CAM) for higher speed data processing. To evaluate system performance, throughput, latency, and memory utilization were measured for different cases using different tools, also the number of rules that an incoming packet is subjected to was varied to get more readings using both software and hardware features. The results showed that the designed firewall system provides better performance than traditional firewalls. System throughput was doubled times of the one with Linux-Iptables firewalls.

Implementation of Artificial Neural Network Controller for Double-Input Boost Converter

Received Mar 3, 2018 Revised Apr 11, 2018 Accepted Apr 21, 2018 Paintball has gained a huge popularity in Malaysia with growing number of tournaments organized nationwide. Currently, Ideal Pro Event, one of the paintball organizer found difficulties to pair a suitable opponent to against one another in a tournament. This is largely due to the manual matchmaking method that only randomly matches one team with another. Consequently, it is crucial to ensure a balanced tournament bracket where eventual winners and losers not facing one another in the very first round. This study proposes an intelligent matchmaking using Particle Swarm Optimization (PSO) and tournament management system for paintball organizers. PSO is a swarm intelligence algorithm that optimizes problems by gradually improving its current solutions, therefore countenancing the tournament bracket to be continually improved until the best is produced. Indirectly, through the development of the system, it is consider as an intelligence business idea since it able to save time and enhance the company productivity. This algorithm has been tested using 3 size of population; 100, 1000 and 10,000. As a result, the speed of convergence is consistent and has not been affected through big population.N. N. S. Abdul Rahman, N.M. Saad, A. R. Abdullah, M. R. M. Hassan, M. S. S. M. Basir, N. S. M. Noor 1,2,4,6Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia 2,3Center for Robotics and Industrial Automation, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia 3,5Faculty of Electrical Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, MalaysiaLight rail transit (LRT), or fast tram is urban public transport using rolling stock similar to a tramway, but operating at a higher capacity, and often on an exclusive right-of-way. Indonesia as one of developing countries has been developed the LRT in two cities of Indonesia, Palembang and Jakarta. There are opinions toward the development of LRT, negative and positive opinions. To reveal the level of LRT development acceptance, this research uses machine learning approach to analyze the data which is gathered through social media. By conducting this paper, the data is modeled and classified in order to analyze the social sentiment towards the LRT development.Mohamad, S., Nasir, F.M., Sunar, M.S., Isa, K., Hanifa, R.M., Shah, S.M., Ribuan, M.N., Ahmad, A. 1,4,6,7,8Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia, Johor, Malaysia 1,2,3UTM-IRDA Digital Media Centre, Media and Game Innovation Centre of Excellence, Universiti Teknologi Malaysia, Johor, Malaysia 1,2,3Faculty of Computing, Universiti Teknologi Malaysia, Johor, Malaysia 5Centre for Diploma Studies, Universiti Tun Hussein Onn Malaysia, Johor, Malaysia 6Research Centre for Applied Electromagnetics, Universiti Tun Hussein Onn Malaysia, Johor, MalaysiaReceived Jan 31, 2018 Revised Apr 21, 2018 Accepted Apr 30, 2018 Bluetooth is an emerging mobile ad-hoc network that accredits wireless communication to connect various short range devices. A single hop network called piconet is the basic communication topology of bluetooth which allows only eight active devices for communication among them seven are active slaves controlled by one master. Multiple piconets are interconnected through a common node, known as Relay, to form a massive network called as Scatternet. It is obvious that the performance of Scatternet scheduling is highly dependent and directly proportionate with the performance of the Relay node. In contrary, by reducing the number of Relays, it may lead to poor performance, since every Relay has to perform and support several piconet connections. The primary focus of this study is to observe the performance metrics that affects the inter-piconet scheduling since the Relay node’s role is like switch between multiple piconets. In this paper, we address and analyze the performance issues to be taken into consideration for efficient data flow in Scatternet based on Relay node.

Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library

This This paper addresses a novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA). Ling’s algorithm is used to optimise the pre-processing blocks (white nodes) and intermediate Generate-Propagate blocks (Black nodes) of the prefix tree to minimise the congestion of wires which contributes to reduction in chip size and to improve performance. The resulting prefix-tree arrangement is then merged into a sequence of modified CSEA. Experimental results show that HPA has speed improvement of 62% and 13% power reduction in comparison of the traditional Carry Look-Ahead Adder (CLA).

Soft Error Mitigation on Dual Rail Latch

A single event upset (SEU) or soft error is defined as a temporary error on digital electronics due to the effect of radiation. Such an error can cause system failure, e.g. a deadlock in an asynchronous system or production of incorrect outputs due to data corruption. With increasing system complexities and integration scale, transistors have become more vulnerable to soft error, necessitating analysis of soft error in circuits, which is the focus of this thesis. Vulnerability of circuits to soft errors is further aggravated by several factors, such as variations in the process and temperatures. Process variations are inaccuracies in the manufacturing process which may lead to deterioration of circuit performance and increase in power consumption. Temperature variation degrades the threshold voltage, carrier mobility and velocity saturation of transistor. As a result of degrading carrier mobility, the drain current becomes lower thus increasing the sensitivity of the node to SEU.

Design of 0.18um high voltage LDMOS for automotive application

Designing of high voltage LDMOS with a reduced surface field (RESURF) structure have been investigated to achieve the optimum figure of merit, maximum breakdown voltage accompanied with low on resistance. The drift region profile and device geometry plays important role to achieve target breakdown voltage of 80 V. The electrical behaviors of the designed high voltage LDMOS for both on state and off state conditions are discussed analytically in this paper.

Fast Processing Multiplier

This paper presenting the alternative binary arithmetic multiplier which constructed by implementing the shift/copy process to serve the partial product generation line with two levels carry lookahead adders (CLAs) to perform the final operands adding in order to speed up the carry propagation along the array. The design is particular structured for 4-bits and 8-bits multiplier for testing purposes. It is then analysis together with the conventional bit array multiplier topology and the comparison has been presented in term of functionality, speed efficiency and area consumption. Both synthesis and simulation of the multipliers are performed in Altera Quartus II, by using fully synthesizable hardware description language in VHDL without any design constraints