Noriyuki Fukushima

High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor

A progressive 1/1.8-inch 1920times1440 CMOS image sensor with a column-inline dual CDS architecture uses a 0.18mum CMOS process. This sensor implements digital double sampling with analog CDS on a column parallel ADC. Random noise is 5.2e-rms and the DR is 68dB at 180frames/s(6.0Gb/s). FPN is <0.5e-rms without the correction circuit

A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor

In recent years, cellphone cameras have come to require much more diversification and increased functionalities, due to the strong growth of the smartphone market. In addition to the image quality, speed, and pixel counts that conventional image sensors require, there is high demand for new functions that can respond to various photo-taking scenes. We developed a stacked CMOS image sensor (CIS), composed of conventional back-illuminated (BI) image-sensor technology and 65nm standard logic technology.

Monolithic Filter and its Application to TV MPX Sound Decoder IC

In addition to giving the best possible picture and sound quality, todays color TV set is also required to absorb all of the reception expansions, such as sound multiplex, teletext, be able to be interfaced with video recorders and videotex, etc. The color TV is expected to do all this without a great increase in cost, and, of course, at a low failure level. The fundamental parts of the color TV system need to be standardized. If the signal processing parts were standardized, dimensions and power consumption decreased, these parts could be used in all sets, even pocket-sized televisions, and the number of engineers working on these fundamental systems could be reduced.

A CMOS 8-bit 20MHz two-step parallel A/D converter with 95mW power consumption

The need for a low-cost, high-speed A/D converter with low power consumption is growing as digital video-signal processing applications in the consumer electronics field increase. Although a flash ADC offers a sufficiently high conversion rate for video applications, it has a high power consumption because of its large number of comparators. The two-step parallel ADC, on the other hand, has significantly fewer comparators, and thus a lower power consumption and, because its chip size is smaller, it can be made at lower cost. A conventional two-step parallel ADC has, however, three problems: a relatively slow conversion rate, a relatively poor differential linearity, and the need for a peripheral sample-and-hold circuit. The authors report a new 8-bit two-step parallel ADC which solves these problems.<<ETX>>