Noriyuki Tanino

A C-band 4-stage low noise miniaturized amplifier using lumped elements

A C-band monolithic four-stage low noise miniaturized amplifier has been developed. It employs lumped elements for the matching circuit to reduce the chip size. In the design of the IC, an integrated CAD system was used to consider parasitic microwave components. The 1.65 mm/spl times/2.30 mm amplifier achieved a gain of over 40 dB with a noise figure of less than 1.7 dB. The amplifier gives a minimum noise figure of 1.54 dB and a gain of 41 dB. A good agreement between measured and simulated data has been achieved.<<ETX>>

A New Practical Harmonics Tune for High Efficiency Power Amplifier

This paper describes a new practical harmonics tune (Tuned B), in which 2nd harmonic is open and 3rd harmonic is short, to realize higher efficiency power amplifiers. Analytic calculations of drain voltage and current waveforms as well as load line are often used for design of high efficiency power amplifiers. When considering up to 3rd order harmonic in these analyses, the Tuned B is more suitable than class F. Simulation results of nonlinear p-HEMT modeling indicated that the proposed Tuned B achieved higher efficiency than that of the class F in gain compression region. Breadboard evaluations using 0.5¿m p-HEMT demonstrated 81.7% maxmum drain efficiency and a power added efficiency (PAE) of 67.5% with an output power (Po) of 30.5dBm at an adjacent channel leakage power (ACP) of ¿48dBc in Japanese personal digital cellular (PDC).

A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature

A GaAs 1 K*4-kb SRAM designed using a novel circuit technology is described. To reduce the temperature dependence and the scattering of the access time, it was necessary to increase the signal voltage swing and to reduce the leakage current in access transistors of unselected memory cells. In the 4-kb SRAM, source-follower circuits were adopted to increase the voltage swing, and the storage nodes of unselected memory cells were raised by about 0.6 V to reduce the subthreshold leakage current in the access transistors. The 4-kb SRAM was fabricated using 1.0- mu m self-aligned MESFETs with buried p-layers beneath the FET regions. A maximum address access time of 7 ns and a power dissipation of 850 mW were obtained for the galloping test pattern at 75 degrees C. Little change in the address access time was observed between 0 and 75 degrees C. >

High gain and high efficiency K-band power HEMT with WSi/Au T-shaped gate

We have developed WSi/Au T-shaped buried gate pseudomorphic HEMT with the good uniformity of recess current by using a selective etching process and with a high off-state break down voltage of over 19 V. A 1.4 W output power has been obtained with a power-added efficiency of 55.6% and an associated gain of 9.2 dB under high voltage operation of Vd=10 V at 18 GHz. This is the highest gain and efficiency achieved by a single FET chip with over a watt output power at this frequency.

A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance R<inf>s</inf>and gate capacitance C<inf>g</inf>, the shallow n⁺implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance g<inf>m</inf>, low source resistance R<inf>s</inf>, small gate capacitance C<inf>g</inf>, and small deviation of threshold voltage<tex>\part V_{th}</tex>, and thus is suitable for high-speed GaAs LSIs. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.

A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure

A digital variable-delay macro cell (DVDM) on a GaAs 100 K-gates gate array has been developed for measurement instruments and for elimination of clock skew on printed circuit boards. Three new technologies for high resolution are introduced into the DVDM: (1) a meshed air bridge structure bringing 29% reduction of propagation delay, (2) a rising edge selector circuit creating 33% decrement of standard deviation /spl sigma/ on delay, and (3) a delay circuit with a discharge control path for a high resolution of 12 ps. The DVDM produces 24.4 ns span and 12 ps resolution, about one-quarter that of a conventional DVDM. Linearity error is less than /spl plusmn/27 ps. Power dissipation of the DVDM is 250 mW/cell, about one-third of the value for a conventional Si bipolar junction transistor analog delay circuit.

A 3.3V, 1W GaAs One-Chip Power Amplifier MMIC for Cellular Phones

A 900-MHz-band 1W one-chip power amplifier MMIC, which operates at the low-supply voltage of 3.3 V and includes all bias and output matching circuits, has been developed for cellular phones. It is capable of delivering output power over 1.1 W with a power added efficiency of 43% at 3.3 V. With its extremely small chip size of 2.5 mm × 3.48 mm, it is less than one fifth the size of previously reported multi-chip ICs (MCICs). This new MMIC, the characteristics of which are compared with those of the existing MCICs, can be expected to contribute to the realization of smaller, lighter-weight cellular phones.

A GaAs 16 K SRAM with a single 1-V supply

A GaAs 4 K/spl times/4-b static random access memory (SRAM) with 11-ns access time and 1-W power dissipation is described. The device is fabricated using 1.0-/spl mu/m WSi/SUB x/ selfaligned gate metal semiconductor FET (MESFET) and double-level interconnection technology. Optimization of fan-out and adoption of an address precoder circuit enable both fast access time and low power dissipation. The SRAM operates with a single 1.0-V supply.

A GaAs LD Driver IC for a 2.5 Gb/s Optical Communication System

A large modulation current laser-diode (LD) driver IC is developed using a GaAs self-aligned gate MESFET with a 0.8 ¿m gate length for a 2.5 Gb/s optical communication system. The IC consists of a level shifter, a two-stage input buffer, a mark density monitor and a current driver. The current driver adjusts the modulation current over 50 mAp-p for a 25 ¿ load using a current mirror circuit. The rise and fall times are 90 ps and 110 ps, respectively. This IC also has small deviation of ±0.2% of the modulation current for the ambient temperature from ¿20 °C to 80 °C. The dispersion penalty of a 100 km length transmission using 1.3 ¿m zero-dispersion fiber with an optical transmitter consisting of this IC and a MQW DFB LD is less than 0.8 dB. The IC is suitable for the practical application to 2.5 Gb/s optical communication systems.

Integrated CAD System for an MMIC using Symbolic Layout

In this paper, a microwave symbolic layout is proposed as an interface between a circuit simulation and a mask pattern. This system is separated from the design of process oriented design rules allowing a designer to design a circuit without understanding the complicated MMIC process. An automatic conversion program has been also developed to convert from a mricrowave symbolic layout to a mask pattern. Using this system, a designer can consistently go from the circuit design operation to the mask data creation.