Norman Chang

Fast thermal coupling simulation of on-chip hot interconnect for thermal-aware EM methodology

For advanced process technologies as in FinFET or FDSOI, the current density increases while the wire width and spacing get reduced, leading to higher ΔT on wires due to self-heating and strong thermal coupling among wires. This impacts chip reliability and performance. Also, since the traditional methodology of using a uniform worst-case temperature across a chip for electromigration (EM) sign-off is often too pessimistic, or could fail to take into account a thermal hotspot, it is necessary to estimate the realistic temperature of wires to ensure reliability while optimizing the wire design. Due to the large number of wires in a modern chip, application of a direct thermal field solution such as FEM (finite element method) with all wires considered is not feasible. On the other hand, this paper describes an innovative method where the temperature increases on millions of wires due to self-heat are efficiently and accurately calculated. Also outlined is the thermal-aware EM methodology that considers both Chip-package-system (CPS) thermal environment and self-heat.

A new full-chip verification methodology to prevent CDM oxide failures

This paper describes a new full-chip CDM ESD verification method that enables the evaluation of complete integrated circuits (ICs) for CDM risk. We demonstrate that a robust analysis must comprehend millions of locations of driver-receiver (D/R) pairs on an IC, an accurate model of the grid resistance and an adequate representation of the CDM current distribution.

Emerging ADAS Thermal Reliability Needs and Solutions

Advanced driver assistance systems (ADASs) used for pedestrian detection, parking assist, night vision, blind-spot monitoring, collision avoidance, and other such capabilities have significantly enhanced car safety and reduced the risk of dangerous accidents. Their further evolution into a network of intelligent systems using vehicle-to-infrastructure (V2I) and vehicle-to-vehicle (V2V) communications is paving the way for autonomous driving. To support these advanced technologies, automotive electronics must be overhauled to enable machine learning capabilities, particularly deep learning, to transform the typical car into a smart system on wheels. Thermal reliability is critical because these high-power, intelligent electronics systems must last more than 10 years under often hostile thermal environments. This article presents an innovative multiphysics solution for thermal, thermal-aware electromigration, and thermal-induced stress analysis of a chip-package-system realized in 3DIC, an example of which is an AI system used in ADAS.

An efficient transient thermal simulation methodology for Power Management IC designs

Power Management devices are becoming ubiquitous in every electronic system for achieving energy efficiency with constrained power/thermal budget. Multi-Function and Multi-Channel PMICs are becoming common design trend to support diverse voltage/power requirements of complex SoCs. In this paper, we present an approach to perform a full chip level thermal analysis with the capability to perform a detailed sub-modeling for electro-thermal analysis with Finite Element method and perform thermal-aware EM and stress analysis. The approach in transient thermal, thermal-aware EM and stress analyses includes the generation of thermal-aware chip power maps, conversion of converged thermal profiles in Power Devices to thermal loadings and detailed sub-modeling of on-chip structures for transient thermal, thermal-aware EM and thermal-induced stress analyses.