Norman Frederick Brickman

Telephony channel simulator for speech recognition application

A telephony channel simulation process is disclosed for training a speech recognizer to respond to speech obtained from telephone systems. An input speech data set is provided to a speech recognition training processor, whose bandwidth is higher than a telephone bandwidth. The process performs a series of alterations to the input speech data set to obtain a modified speech data set. The modified speech data set enables the speech recognition processor to perform speech recognition on voice signals from a telephone system.

Instantaneous context switching for speech recognition systems

An instantaneous context switching speech recognition system is disclosed which enables a speech recognition application to be changed without loading new pattern matching data into the system. Selectable pointer maps are included in the memory of the system which selectively change the relationship between words and phonemes between a first application context and the pattern matching logic to a second application context and the pattern matching logic.

Word autocorrelation redundancy match (WARM) technology

Word Autocorrelation Redundancy Match (WARM) is an intelligent facsimile technology which compresses the image of textual documents at nominally 145:l by use of complex symbol matching on both the word and character level. At the word level, the complex symbol match rate i s enhanced by the redundancy of the word image. This creates a unique image compression capability that allows a document to be scanned for the I50 most common words, which make up roughly 50% of the text by usage, and upon their match the words are replaced for storageltransmission by a word identification number. The remaining text is scanned to achieve compaction at the character level and compared to both a previously stored library and a dynamically built library of complex symbol (character) shapes. Applying the complex symbol matching approach at both the word and character levels results in greater efJiciency than is achievable by state of the art CCITT methods.

Hardware implementation of a small system in programmable logic arrays

Large Scale Integration, LSI, is the means by which digital circuits have achieved remarkable manufacturing cost reductions but, unfortunately, at the expense of higher engineering design costs. Programmable Logic Arrays, PLAs, exploit many of the benefits of LSI but without the high engineering design costs. This paper describes an experiment in the design and implementation of a small complex system in array logic. The IBM 7441 Buffered Terminal Control Unit was selected for this comparison because it is a small but complex terminal controller implemented in dual in-line packaged transistor logic, DIP-TL, with small to medium scale integration.