Nour-Eddine Bouguechal

CONTRIBUTION TO THE ANALYSIS AND MODELING OF THE NON-IDEAL EFFECTS OF PIPELINED ADCs USING MATLAB

The present work analyses the non-ideal effects of pipelined analog-to-digital converters (ADCs), also sometimes referred to as pipeline ADCs, including the non-ideal effects in operational amplifiers (op-amps or OAs), switches and sampling circuits. We study these nonlinear effects in pipelined ADCs built using CMOS technology and switched-capacitor (SC) techniques. The proposed improved model of a pipelined ADC includes most of the non-idealities which affect its performance. This model, simulated using MATLAB, can determine the basic blocks specifications that allow the designer to meet given data converter requirements.

7.72 ppm/°C, ultralow power, high PSRR CMOS bandgap reference voltage

This paper describes a CMOS bandgap reference fabricated in 0.18μm TSMC CMOS technology, with ultralow power consumption, high Power Supply Rejection Ratio (PSRR) and less temperature drift over wide temperature range. This is achieved by using a straightforward 3 bits trimming circuit design includes high ohmic polysilicon unit resistors to save area and 8 to 1 multiplexer digitally controlled to switch between the 8 different outputs. The performance of the design was verified experimentally. The implemented bandgap reference voltage measured has showed a temperature coefficient of 7.72 ppm/°C over temperature range of -40°C to 125°C on wide supply voltage from 2.6V to 4V and consumes a supply current of 1.054μA at 4V, PSRR of -62dB at 1GHz are easily achieved, which make it widely applicable in portable equipment. The active area of the circuit is 0.1 mm2.

Multi-Objective Genetic Algorithm optimization of CMOS operational amplifiers

This work studies the problem of CMOS operational amplifiers (op-amps) optimization. A front Pareto based-MOGA (Multi-Objective Genetic Algorithm) methodology is proposed to optimize the operational amplifier. The proposed approach is used to find the optimal dimensional transistor parameters in order to obtain operational amplifier performances for analog and mixed CMOS-based circuit applications. To evaluate the proposed approach, an example in both time and frequency domains for a two-stage CMOS Operational Transconductance Amplifier (OTA) is presented in 0.18μm process. The simulation results confirm the efficiency of MOGA in determining the device sizes in an analog circuit.

Indoor Mobile Robot Local Path Planner with Trajectory Tracking

This paper deals with the design and implementation of an indoor mobile robot local path planner. This latter is based essentially on an ultrasonic perception system, where the covered region of sight is widened and the apparent distance between any two adjacent sensors can be adjusted. So, good resolution can be obtained and laterally positioned obstacles with respect to the robot line of sight are well identified. Furthermore, we propose a technique to improve the odometric method, to reduce the systematic errors and to detect floor irregularities. Following a predefined trajectory is provided by the control of the trailing wheel deviation angle.

A Programmable Voltage Reference Dsign

The paper emphasizes the circuit innovations of a key analog function realized on the IAD GmbH DLC_2 family chip, a precision programmable voltage reference with superior performance capabilities dedicated for an integrated 10 bits D/A converter. The chip developed in co-operation of IAD and MAZ Brandenburg has been produced with 0.35 mum CMOS switched capacitor technology from AMS, it can be used on the one hand within typical power-line applications, such us controlling and management, and the other hand for data communication, such as telephony or internet access. The programmable voltage reference is based on a new design that provides fast programmability between voltages and stable voltage operation from 0.25 Vdda to 0.75 Vdda. The main objective is to select a design that meets as close as possible criteria related to the chip specification requirements such as reliability, flexibility, and integration area. Consequently, an adequate programmable voltage reference is proposed which is 4 bits decoder-based converter architecture

GA-based modeling of a non-ideal second order low-pass ΣΔ modulator

An approach is presented for the high-level simulation and synthesis of discrete-time modulators based on a simulation-based optimization strategy. The high-level synthesis approach determines both the optimum modulator topology and the required building block specifications, such that the system specifications mainly signal to noise ratio (SNR). A genetic-based differential evolution algorithm is used in combination with a fast dedicated behavioral simulator to realistically analyze and optimize the modulator performance. The approach has been implemented in a MATLAB Optimization tool. Simulation results are shown for both the analysis and optimization capabilities, illustrating the effectiveness of the approach. The selected range of optimized modulator topologies as a function of the modulator specifications for a wide range of values indicate the capabilities of and the performance range covered by the tool.

Modeling of op-amp nonlinearities in pipelined ADC

In this paper, we present a behavioral SIMULINK model for the simulation of operational amplifiers (op-amp). The model includes most of the nonlinearities which affect the performance of these circuits, such parameters (noise, finite gain, finite bandwidth, and slew-rate).With the proposed models it is possible to accurately predict with fast simulations the linearity of sample and hold (Stll) circuit and Multiply digital-to-analog (MDAC) circuit that constructed the pipelined ADC.

Design of a reference voltage for A/D converters

This paper discusses the successful implementation of a reference voltage circuit tailored to the needs the IAD GmbH DLC_2 family chip, which commonly encounter the demand for two high precision and high stability outputs; positive reference voltage vrefp and negative reference voltage vrefn, which define the dynamic range of the input signal of a successive approximation A/D converter. The chip developed in co-operation of IAD and MAZ Brandenburg, for power-line applications. The reference voltage circuit has been designed and fabricated using 0.35 mum CMOS switched capacitor double poly technology from AMS, and occupies a total area of only 0.084 mm2. Simulations show that the voltages are well settled during the total conversion time. The circuit is capable of driving a 2.2 muF capacitor load at 25 MHz clock frequency while consuming 22 mW of power from a 3.3 V supply voltage.

A charge redistribution SAR ADC for a pressure correction ASIC

A charge redistribution successive approximation register analog-to-digital converter (SAR ADC) targeted for use in a pressure correction ASIC is presented. The ASIC finds a large field of applications in automotive industry, where aggressive conditions of operation, such as big temperature and supply variations, are met. It is therefore necessary for the ADC to ensure good linearity with respect to temperature and supply in the entire interval of operation. This paper describes the design and implementation of an 11-bits, 25 KS/s SAR ADC to meet the unique requirements of digitization of the ASIC. The reported ADC consumes 1 mW at 5 Volts supply and 1 MHz clock. It is designed in the ELMOS 0.8 mum high voltage BiCMOS technology.