O. Ait Mohamed

Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications

SRAM-based FPGAs are increasingly popular in the aerospace industry for their field programmability and low cost. However, they suffer from cosmic radiation induced Single Event Upsets (SEUs), commonly known as soft errors. In safety-critical applications, the dependability of the design is a prime concern since failures may have catastrophic consequences. An early analysis of dependability of such safety-critical applications will enable designers to develop a design that meets the high availability and reliability requirements of the DO-254 standard. This paper introduces a novel methodology based on probabilistic model checking, to analyze the dependability properties of safety-critical systems and to suggest required mitigation techniques, such as Triple Modular Redundancy (TMR) or TMR with less frequent scrubs for early design decisions. Starting from a high-level description of a system, a Markov model is constructed from the Control Data Flow Graph (CDFG) expressing the functionality and from failure/mitigation parameters for the targeted FPGAs. Such an exhaustive model captures all the failures and repairs possible in the system within the radiation environment. We present a case study on a benchmark circuit to illustrate the applicability of the proposed approach to demonstrate that a wide range of useful dependability properties can be analyzed using our proposed methodology.

TBCD-TDM: Novel Ultra-Low Energy Protocol for Implantable Wireless Body Sensor Networks

The field of Remote health monitoring now includes technologies such as home and mobile health monitoring, tele-retinal imaging, tele-radiology, remote cardiac monitoring, video conferencing and sensors for remote diagnosis and treatment to patients. In this regard, implantable wireless body sensor networks (IWBSNs) have recently emerged as an important and growing research area. These implantable sensors are required to be reliable, very small, battery-operated, and capable of collecting data, processing it, and transmitting it wirelessly and efficiently. Since these devices are required to run with limited resources (energy, processing, and memory), their utility protocols (collecting, processing, and communication) should be designed carefully, not only to work reliably but, more importantly, to be resource-efficient. The life time of the embedded batteries associated with these sensor nodes varies from a few days to a few weeks as was described in a previous work by the authors. In this paper, we propose a novel technique which allows the implanted sensor nodes to communicate with a base station located outside the body efficiently by consuming the minimum amount of energy. Our proposed protocol allows the battery to last significantly longer even for years with a gain of up to 100s times of power saving. This will improve the quality of patient life, and reduce risk of infection resulting from frequent chirurgical operations needed to replace such implantable batteries. Also, a new time synchronization algorithm is briefly introduced in this work that is especially applicable to our proposed communication protocol.

Performance analysis of constraint solvers for coverage directed test generation

Constraint random testing (CRT) is the most common verification technique used nowadays. Coverage driven constraint random test generation (CDTG) is a methodology based on CRT. In this methodology, constraints which give maximum coverage are used to randomly generate input stimuli for testing. The efficiency of CDTG depends on the technique used to generate the automated feedback path and on the constraint solver used. In this paper, a comparative study is conducted to measure the effectiveness of VCS2009.06 against other commercially available constraint solvers. Our results are obtained by solving N Queens problem and car sequencing problem using the different solvers.

A New Approach for the Construction of Multiway Decision Graphs

Multiway Decision Graphs (MDGs) are a canonical representation of a subset of many-sorted first-order logic. It generalizes classical BDDs with abstract data and uninterpreted functions. In this paper, we describe a new MDG construction based on the Generalized-If-Then-Else (GITE) operator. Consequently, we review the main algorithms used for verification techniques i.e. relational product and pruning by subsumption. Unlike an earlier version of the MDG package, basic MDG algorithms are defined uniformly through this single GITE operator which will lead to a more efficient implementation. The new tool, called NuMDG, accepts an extended SMV language, supporting abstract data sorts.

Design of a C-element based clock domain crossing interface

Circuit failures due to metastability and single event transients are increasing in deep sub-micron technology. Technology scaling is also causing degradation in reliability of bi-stable circuits. Synchronization circuits that are robust to metastability are important especially with the increased use of multi-clock domain designs in SoCs. In this paper, we address the design and verification of clock domain crossing interfaces (CDCs) that connect mutually asynchronous clock domains. We propose the use of C-element based synchronizers in clock domain crossing interfaces. In order to enhance the Mean Time Between Failures (MTBF) of the interface, a new C-element design with an improved metastability recovery time is proposed. The new design is implemented in 90nm CMOS technology and simulated using SPICE.

Delay calculation and error compensation in TBCD-TDM communication protocol for Wireless Body Sensor Networks

Implantable sensor network becomes nowadays an important area of research. Sensors are implanted inside the patient body to measure its physiological changes and send them wirelessly to an external close-by device. Such network is called IWBSN (Implantable Wireless Body Sensor Network). The life time of the embedded batteries associated with these tiny sensor nodes is too short. Hence power consumption is the most important design metrics associated with these sensors. A novel ultra low energy communication protocol has been proposed to address the life time of the battery within the sensor. Our proposed protocol is based on time synchronization between all sensor nodes and the base station, where the delay of the wireless signal propagation is very critical. Tracking of the time synchronization using the standard algorithms is very costly energy-wise. In this paper, we propose a technique which automatically calculates the delay (sensor-node to Base-station) and compensates for any discrepancies. This correction is done while saving the tiny energy resources inside the sensor nodes. Our proposed solution has been tested wirelessly through transceiver boards using a single FPGA board. The experimental results have shown the correctness of our protocol along with the delay correction technique.

An automated SAT encoding-verification approach for efficient model checking

In this paper, we introduce an automated conversion-verification methodology to convert a Directed Formula (DF) into a Conjunctive Normal Form (CNF) formula that can be fed to a SAT solver. In addition, the formal verification of this conversion is conducted within the HOL theorem prover. Finally, we conduct experimental results with different-sized formulas to show the effectiveness of our methodology.

SAT based model checking for MDG models

Multiway Decision Graph (MDG) is a canonical representation of a subset of many-sorted first-order logic. It generalizes the logic of equality with abstract types and uninterpreted function symbols. The area of Satisfiability (SAT) ha s been the subject of intensive research in recent years, with significant theoretical and practical contributions. From a practical perspective, a large number of very effective SAT solvers have recently been proposed, most of which based on improvements made to the original Davis-Putnam algorithm. Local search algorithms have allowed solving extremely large satisfiable instances of SAT. The combination between various verification methodologies will enhance the capabilities of each and overcome their limitations. In this paper, we introduce a model checking methodology for MDG based models using MDG tool and SAT solver. We use SAT solver searching for feasible paths of reachable states satisfying the property under certain encoding constraints. Finally, we provide a case study showing the correctness and the efficiency of our approach.

The performance of combining multiway decision graphs and HOL theorem prover

In this paper, we are interested in defining a platform for high level model checking using multiway decision graphs (MDGs) within high order logic. The platform is based on the logical formulation of an MDG as a directed formulae (DF). The DF is defined in the HOL theorem prover where the many sorted first-order logic is characterized as a HOL built-in data type. Then, the HOL inference rules are defined to check the well-formedness conditions of any directed formula. Based on this formalization, the MDGs operations are defined as inference rules and consistency and well-formedness proof of each operation is provided. Finally, some experimental results are presented to show the performance of the MDG-HOL platform. The obtained results show that this platform offers a considerable gain in terms of automation without sacrificing CPU time and memory usage.

A methodology to generate evenly distributed input stimuli by clustering of variable domain

Constrained Random Verification (CRV) is becoming the mainstream methodology for the functional verification of complex System on Chip (SoC) designs. In order to achieve verification closure, CRV tools have to produce a large number of solutions, evenly distributed, in the search space. To attain this requirement, we propose a technique which analyzes the solution space by using consistency algorithm and splits the variables domain into clusters. The proposed technique helps to generate input stimuli which are evenly distributed in search space. The proposed technique has been validated through experimental results. Experimental results show that the proposed methodology guarantees evenly distributed stimuli and improves by about 15% the veriication coverage.