Octavio Nieto-Taladriz

A project-based learning approach to design electronic systems curricula

This paper presents an approach to design Electronic Systems Curricula for making electronics more appealing to students. Since electronics is an important grounding for other disciplines (computer science, signal processing, and communications), this approach proposes the development of multidisciplinary projects using the project-based learning (PBL) strategy for increasing the attractiveness of the curriculum. The proposed curriculum structure consists of eight courses: four theoretical courses and four PBL courses (including a compulsory Masters thesis). In PBL courses, the students, working together in groups, develop multidisciplinary systems, which become progressively more complex. To address this complexity, the Department of Electronic Engineering has invested in the last five years in many resources for developing software tools and a common hardware. This curriculum has been evaluated successfully for the last four academic years: the students have increased their interest in electronics and have given the courses an average grade of more than 71% for all PBL course evaluations (data extracted from students surveys). The students have also acquired new skills and obtained very good academic results: the average grade was more than 74% for all PBL courses. An important result is that all students have developed more complex and sophisticated electronic systems, while considering that the results are worth the effort invested

Improving network security using genetic algorithm approach

With the expansion of Internet and its importance, the types and number of the attacks have also grown making intrusion detection an increasingly important technique. In this work we have realized a misuse detection system based on genetic algorithm (GA) approach. For evolving and testing new rules for intrusion detection the KDD99Cup training and testing dataset were used. To be able to process network data in real time, we have deployed principal component analysis (PCA) to extract the most important features of the data. In that way we were able to keep the high level of detection rates of attacks while speeding up the processing of the data.

Wireless Measurement System for Structural Health Monitoring With High Time-Synchronization Accuracy

Structural health monitoring (SHM) systems have excellent potential to improve the regular operation and maintenance of structures. Wireless networks (WNs) have been used to avoid the high cost of traditional generic wired systems. The most important limitation of SHM wireless systems is time-synchronization accuracy, scalability, and reliability. A complete wireless system for structural identification under environmental load is designed, implemented, deployed, and tested on three different real bridges. Our contribution ranges from the hardware to the graphical front end. System goal is to avoid the main limitations of WNs for SHM particularly in regard to reliability, scalability, and synchronization. We reduce spatial jitter to 125 ns, far below the 120 μs required for high-precision acquisition systems and much better than the 10-μs current solutions, without adding complexity. The system is scalable to a large number of nodes to allow for dense sensor coverage of real-world structures, only limited by a compromise between measurement length and mandatory time to obtain the final result. The system addresses a myriad of problems encountered in a real deployment under difficult conditions, rather than a simulation or laboratory test bed.

Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops

Traditional approaches for fixed-point characterization are based on long simulations or additive noise models that do not show the nonlinear behavior of the quantization operations in reasonable time. In this paper, a novel interval-based approach that provides both tighter and faster results than the existing approaches is presented. It is based on a nonlinear adaptation of the quantization operations of affine arithmetic (AA). The results obtained with this method are compared to other published interval-based approaches, and the problem of interval oversizing is discussed in detail. Simulations show that: 1) the propagation techniques are not well suited to characterize the quantized linear systems with feedback loops; 2) the AA provides oversized bounds in this type of systems; and 3) the proposed adaptation does not provide guaranteed bounds as in the traditional interval-based computations, but it provides tighter estimates of the evolution in time of the ranges of the fixed-point signals and better runtime than the existing interval-based characterization techniques.

Finding an internal state of RC4 stream cipher

The RC4 is a stream cipher widely deployed in software applications due to its simplicity and efficiency. The paper presents a cryptanalytic attack that employs the tree representation of this cipher and introduces an abstraction in the form of general conditions for managing the information about its internal state. In order to find the initial state, the tree of general conditions is searched applying the hill-climbing strategy. The complexity of this attack is lower than that of an exhaustive search. The attack is derived from a general cryptanalytic approach for a class of table-shuffling ciphers, whose next-state function permutes the table entries. Incorporating the general conditions in the existing backtracking algorithm, the estimated complexity of the cryptanalytic attack is decreased below the best published result but the RC4 still remains a quite secure cipher in practice.

Fast and accurate computation of the roundoff noise of linear time-invariant systems

From its introduction in the last decade, affine arithmetic (AA) has shown beneficial properties to speed up the time of computation procedures in a wide variety of areas. In the determination of the optimum set of finite word-lengths of the digital signal processing systems, the use of AA has been recently suggested by several authors, but the existing procedures provide pessimistic results. The aim is to present a novel approach to compute the round-off noise (RON) using AA which is both faster and more accurate than the existing techniques and to justify that this type of computation is restricted to linear time-invariant systems. By a novel definition of AA-based models, this is the first methodology that performs interval-based computation of the RON. The provided comparative results show that the proposed technique is faster than the existing numerical ones with an observed speed-up ranging from 1.6 to 20.48, and that the application of discrete noise models leads to results up to five times more accurate than the traditional estimations.

Bit-width selection for data-path implementations

Specifications of data computations may not necessarily describe the ranges of the intermediate results that can be generated. However, such information is critical to determine the bandwidths of the resources required for a data-path implementation. We present a novel approach based on interval computations that provides, not only guaranteed range estimates that take into account dependencies between variables, but estimates of their probability density functions that can be used when some truncation must be performed due to constraints in the specification. Results show that interval based estimates are obtained in reasonable times and are more accurate than those provided by independent range computation, thus leading to substantial reductions in area and latency of the corresponding data-path implementation.

Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits

In this brief, we address the combined application of word-length allocation and architectural synthesis of linear time-invariant digital signal processing systems. These two design tasks are traditionally performed sequentially, thus lessening the overall design complexity, but ignoring forward and backward dependencies that may lead to cost reductions. Mixed integer linear programming is used to formulate the combined problem and results are compared to the two-step traditional approach.

Improving security in WMNs with reputation systems and self-organizing maps

One of the most important problems of WMNs, that is even preventing them from being used in many sensitive applications, is the lack of security. To ensure security of WMNs, two strategies need to be adopted: embedding security mechanisms into the network protocols, and developing efficient intrusion detection and reaction systems. To date, many secure protocols have been proposed, but their role of defending attacks is very limited. We present a framework for intrusion detection in WMNs that is orthogonal to the network protocols. It is based on a reputation system, that allows to isolate ill-behaved nodes by rating their reputation as low, and distributed agents based on unsupervised learning algorithms (self-organizing maps), that are able to detect deviations from the normal behavior. An additional advantage of this approach is that it is quite independent of the attacks, and therefore it can detect and confine new, previously unknown, attacks. Unlike previous approaches, and due to the inherent insecurity of WMN nodes, we assume that confidentiality and integrity cannot be preserved for any single node.

FPGA ACCELERATION FOR DNA SEQUENCE ALIGNMENT

In this paper, we present two new hardware architectures that implement the Smith–Waterman algorithm for DNA sequence alignment. Previous low-cost approaches based on Field Programmable Gate Array (FPGA) technology are reviewed in detail and then improved with the goal of increased performance at the same cost (i.e., area). This goal is achieved through low level optimizations aimed to adapt the systolic structure implementing the algorithm to the regular structure of FPGAs, essentially finding the optimum granularity of the systolic cells. The proposed architectures achieve processing rates close to 1 Gbps, clearly outperforming previous approaches. Comparing to the reported FPGA results of the computation of the edit-distance between two DNA sequences, throughput is doubled for the same clock frequency with a minimum area penalty. The design has been implemented on an FPGA-based prototyping board integrated into a bioinformatics system. This has allowed validating the approach in a real system (i.e., including I/O and database access), and comparing the proposed hardware solution to purely software approaches. As shown in the paper, the results are outstanding even for slow-rate buses.