Oh-Suk Kwon

A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications

A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm/sup 2/ die size and a 0.044-/spl mu/m/sup 2/ effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-V/sub CC/ in order to avoid program disturbance issues.

A novel booster plate technology in high density NAND flash memories for voltage scaling-down and zero program disturbance

The booster plate in NAND flash memory cells gives numerous advantages: the reduction of program, erase and pass voltages, zero program disturbance and increased cell current. At the same time, it is simple to integrate the technology to the conventional fabrication processes. It is expected that the booster plate technology will become one of the key technologies for achieving high density memories such as 256 Mbit and 1 Gbit NAND flash.

A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory

We have developed a new 3-bit programming algorithm of high performance TLC(Triple-level-cell, 3-bit/cell) NAND flash memories for 20nm node and beyond. By using the proposed 3-bit algorithm based on reprogramming with SLC-to-TLC migration, performance and BER is improved by 50% and 68%, respectively, compared to conventional method. The proposed algorithm is successfully implemented in 21nm 64Gb TLC NAND flash product that provides 8MB/s write and 400MB/s read throughputs.

A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology

Recently, the demand for 3b/cell NAND flash has been increasing due to a strong market shift from 2b/cell to 3b/cell in NAND flash applications, such as USB disk drives, memory cards, MP3 players and digital still cameras that require cost-effective flash memory. To further expand the 3b/cell market, high write and read performances are essential [1]. Moreover, the device reliability requirements for these applications is a challenge due to continuing NAND scaling to sub-30nm pitches that increases cell-to-cell interference and disturbance. We present a high reliability 64Gb 3b/cell NAND flash with 7MB/s write rate and 200Mb/s asynchronous DDR interface in a 20m-node technology that helps to meet the expanding market demand and application requirement.

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].

A 159mm 2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface

Providing both low cost and high storage capacity by means of device scaling and multi-level cell has been a fundamental feature in developing of NAND flash memory to meet an ever-growing flash market. Recently, however, a high speed interface like DDR (Double Data Rate) was newly adopted in NAND flash to satisfy the requirement of emerging market such as SSD (Solid-State Disk) application where high read and write throughputs are demanded [1]. In addition, as NAND scaling further, a portion of data loading and data out times in overall NAND flash performance has been increased due to increasing page size from 2K to 8K bytes, and even up to 16K bytes at two-plane operation. It significantly affects overall performance degradation in not only SSD but also conventional flash card system. The high speed interface in NAND flash, however, causes to increase chip size because of multiple memory planes more than two and additional signal buses [1]. Therefore, a high speed data interface capability with minimized chip size penalty is required in DDR NAND flash. This paper presents 159mm2 32Gb MLC NAND flash which is capable of 200MB/s read and 12MB/s write throughputs in a 32nm technology.

Development of integrated and interactive spatial planning system of assembly blocks in shipbuilding

As the shipbuilding industry expands, accurate and efficient planning and scheduling of the production process is becoming increasingly important and complex. The availability of space and load in workshops should thus be examined in scheduling the production process. The variety of material, facilities, and information resources makes the spatial planning difficult. In the present work, a spatial planning and scheduling system is developed to support spatial planning and scheduling in block assembly shops, and the workload balance of workshops. The requirements and functions of the system are described and functional components are designed and implemented, based on an object-oriented methodology. The integrated environment is presented in this paper. This system can be expanded to any workshop that requires spatial planning and scheduling.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

A 1.8 V 2 Gb NAND flash memory for mass storage applications

A 1.8 V 2 Gb NAND flash memory is fabricated in a 90 nm process resulting in a 141 mm/sup 2/ die and a 0.044 /spl mu/m/sup 2/ effective cell. To achieve the high level of integration, critical layers are patterned with KF photolithography and phase-shift masks with proximity correction.

Process integration for the high speed NAND flash memory cell

The high speed NAND flash memory cell with a read access time of 80 ns has been demonstrated. In the process integration of the high speed cell, complementary polycide bit lines with the ground selection scheme, self-aligned field through implantation, and metal source line have been introduced. The reliable high speed NAND cell operation has been achieved by enhanced sensing voltage swing, increased cell current and reduced bit line loading.