Olaf Krüger

Laser-assisted processing of VIAs for AlGaN/GaN HEMTs on SiC substrates

Vertical interconnect accesses (VIAs) were fabricated between the source electrode on the front and the ground on the backside of high-power microwave AlGaN/GaN high-electron mobility transistors (HEMTs) on /spl sim/400-/spl mu/m-thick silicon carbide substrates. Through-wafer microholes with an aspect ratio of up to /spl sim/ 8 were drilled using pulsed UV-laser machining and subsequently metallized using electroplating. The successful implementation of the laser-assisted VIA technology into device processing was proven by dc and RF characterization. When biased at 26 V, a saturated output power of 41.6 W with an associated power-added efficiency of 55% at 2 GHz was achieved for a 20-mm AlGaN/GaN HEMT with through-wafer VIAs.

UV laser drilling of SiC for semiconductor device fabrication

Pulsed UV laser processing is used to drill micro holes in silicon carbide (SiC) wafers supporting AlGaN/GaN transistor structures. Direct laser ablation using nanosecond pulses has been proven to provide an efficient way to create through and blind holes in 400 µm thick SiC. When drilling through, openings in the front pads are formed, while blind holes stop ~40 µm before the backside and were advanced to the electrical contact pad by subsequent plasma etching without an additional mask. Low induction connections (vias) between the transistors source pads and the ground on the backside were formed by metallization of the holes. Micro vias having aspect ratios of 5-6 have been processed in 400 µm SiC. The process flow from wafer layout to laser drilling is available including an automated beam alignment that allows a positioning accuracy of ±1 µm with respect to existing patterns on the wafer. As proven by electrical dc and rf measurements the laser-assisted via technologies have successfully been implemented into fabrication of AlGaN/GaN high-power transistors.

Flip-Chip Interconnects for 250 GHz Modules

With the increasing availability of MMICs at frequencies beyond 100 GHz low-loss interconnects for module fabrication in this frequency range become essential. This letter presents results on a flip-chip mounting approach exhibiting a bandwidth of more than 250 GHz, supporting both coplanar and stripline transitions. The interconnects are realized with 10 μm-diameter AuSn microbumps. S-parameter measurements show an insertion loss of less than 1.0 dB per interconnect and a return loss better than 10 dB up to 250 GHz. The experimental results are in good agreement with 3-D EM simulations.

Surface preparation and patterning by nano imprint lithography for the selective area growth of GaAs nanowires on Si(111)

The selective area growth of Ga-assisted GaAs nanowires (NWs) with a high vertical yield on Si(111) substrates is still challenging. Here, we explore different surface preparations and their impact on NW growth by molecular beam epitaxy. We show that boiling the substrate in ultrapure water leads to a significant improvement in the vertical yield of NWs (realizing 80%) grown on substrates patterned by electron-beam lithography (EBL). Tentatively, we attribute this improvement to a reduction in atomic roughness of the substrate in the mask opening. On this basis, we transfer our growth results to substrates processed by a technique that enables the efficient patterning of large arrays, nano imprint lithography (NIL). In order to obtain hole sizes below 50 nm, we combine the conventional NIL process with an indirect pattern transfer (NIL-IPT) technique. Thereby, we achieve smaller hole sizes than previously reported for conventional NIL and growth results that are comparable to those achieved on EBL patterned substrates.

Multifinger Indium Phosphide Double-Heterostructure Transistor Circuit Technology With Integrated Diamond Heat Sink Layer

The RF power output of scaled subterahertz and terahertz indium phosphide double-heterostructure bipolar transistors (InP DHBTs) is limited by the thermal device resistance, which increases with the geometrical frequency scaling of these devices. We present a diamond thin-film heat sink process aimed at the efficient removal of the heat generated in submicrometer InP HBTs. The thin-film diamond is integrated in a wafer bond process. Vertical connections are facilitated by plasma-processed contact holes through the diamond layer, metallized with electroplated gold. The process is suitable for monolithic circuit integration, amenable to the realization of high-power analog circuits in the millimeter-wave region and beyond. The thermal resistance of double-finger transistors with a 0.8-μm emitter width could be reduced to 0.7 K/mW, while reaching the gain cutoff frequencies of fT = 360 GHz and fmax = 350 GHz. An integrated two-stage power amplifier with four-way power combining fabricated in this technology exhibited 20-dBm power output at 90 GHz with a bandwidth of 10 GHz.

Silicon nitride stop layer in back-end-of-line planarization for wafer bonding application

We introduce an approach that combines a 3” InP-DHBT transferred-substrate process with a SiGe-BiCMOS process. First, silicon and InP wafers are processed separately in different fabs. The silicon wafer runs through the complete 0.25 μm BiCMOS production process with five metal layers aluminum/tungsten back-end-of-line using silicon dioxide as dielectric. The processing was adapted for the following wafer bond process by planarization of the topmost metal level. This process flow was improved by using a SiN CMP stop layer on top of the metal layer stack, comparable to trench fill planarization. In that way a low surface topography was reached, this guarantees proper bonding results. Different mm-wave circuits operating at frequencies up to 246 GHz were produced to demonstrate the capability of the process flow.

Diameter evolution of selective area grown Ga-assisted GaAs nanowires

Tapering of vapour-liquid-solid (VLS) grown nanowires (NWs) is a widespread phenomenon resulting from dynamics of the liquid droplet during growth anddirect vapour-solid (VS) growth on the sidewall. To investigate both effects in ahighly controlled way, we developed a novel two-step growth approach for the selective area growth (SAG) of GaAs nanowires (NWs) by molecular beam epitaxy. In this growth approach optimum growth parameters are provided for thenucleation of NWs in a first step and for the shape variation during elongationin a second step, allowing NWs with a thin diameter (45 nm) and an untapered morphology to be realized with high vertical yield. We quantify the flux dependenceof radial VS growth and build a model that takes into account diffusion on theNW sidewalls to explain the observed VS growth rates. As our model is consistent with axial VLS growth we can combine it with an existing model for the diameter variation due to the droplet dynamics at the NW top. Thereby, we achieve fullunderstanding of the diameter of NWs over their entire length and the evolutionof the diameter and tapering during growth. We conclude that only the combinationof droplet dynamics and VS growth results in an untapered morphology. This result enables NW shape engineering and has important implications for doping of NWs.

Mid-infrared beam splitter for ultrashort pulses

A design is presented for a beam splitter suitable for ultrashort pulses in the mid-infrared and terahertz spectral range consisting of a structured metal layer on a diamond substrate. Both the theory and experiment show that this beam splitter does not distort the temporal pulse shape.

Manufacturable Low-Cost Flip-Chip Mounting Technology for 300–500-GHz Assemblies

We developed a chip mounting technology suitable for low-cost assemblies in the 300–500-GHz frequency range, compatible with standard chip and submount fabrication techniques. The waveguide and transition designs are compatible with indium phosphide heterobipolar transistor millimeter-wave monolithic integrated circuit chip architecture. Increased conductor shielding in different multilayer thin-film waveguide topologies is applied to suppress radiative losses, enabling low-loss interconnects up to 500-GHz bandwidth. Standard flip-chip align-and-place equipment is used to assemble the chips onto submounts. Losses are evaluated by banded

Process robustness and reproducibility of sub-mm wave flip-chip interconnect assembly

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