Olga Tveretina

A Decision Procedure for Equality Logic with Uninterpreted Functions

The equality logic with uninterpreted functions (EUF) has been proposed for processor verification. A procedure for proving satisfiability of formulas in this logic is introduced. Since it is based on the DPLL method, the procedure can adopt its heuristics. Therefore the procedure can be used as a basis for efficient implementations of satisfiability checkers for EUF. A part of the introduced method is a technique for reducing the size of formulas, which can also be used as a preprocessing step in other approaches for checking satisfiability of EUF formulas.

An exponential lower bound on OBDD refutations for pigeonhole formulas

ACAC 2009 is organized by the Athens University of Economics and Business (AUEB) and it is the fourth in a series of meetings that aim to bring together researchers working on all areas of the theory of algorithms and computational complexity. These meetings are expected to serve as a lively forum for presenting results that are in a preliminary stage or have been recently presented in some major conference. For the first time this year all submitted papers were reviewed and ACAC also offered to the authors the choice of publishing their contribution (provided it has not been published anywhere else before) with the post-proceedings of EPTCS (Electronic Proceedings in Theoretical Computer Science).

A Proof System and a Decision Procedure for Equality Logic

Equality Logic with uninterpreted functions is used for proving the equivalense or refinement between systems (hardware verification, compiler translation, etc). Current approaches for deciding this type of formulas use a transformation of an equality formula to the propositional one of larger size, and then any standard SAT checker can be applied. We give an approach for deciding satisfiability of equality logic formulas (E-SAT) in conjunctive normal form. Central in our approach is a single proof rule called ER. For this single rule we prove soundness and completeness. Based on this rule we propose a complete procedure for E-SAT and prove its correctness. Applying our procedure on a variation of the pigeon hole formula yields a polynomial complexity contrary to earlier approaches to E-SAT.

Modular Development of Hybrid Systems for Verification in Coq

In this paper we present a formalization of the theory of hybrid automata and algorithms for building trajectory trees using module types and functors in the Coqproof assistant.

Analyzing Separation of Duties Constraints with a Probabilistic Model Checker

Separation of Duties (SoD) is the concept that conflicting activities cannot be assigned to the same individual. A goal of SoD is to separate roles and responsibilities to reduce the risk of fraud or error. We consider the problem of verifying SoD constraints in the presence of uncertain information. We demonsrate the feasibility of implementing probabilistic model checking in a business process design with a case study. Modeling and verification is done with the probabilistic model checker PRISM.

Probabilistic Model Checking of Constraints in a Supply Chain Business Process

Business process models represent corporate activities, their dependencies and relations, as far as they are needed to reach a specific company goal. In practice, they often exhibit stochastic behavior, e.g., to deal with uncertain information. In this paper, we consider the problem of verifying properties over business processes that deal with such uncertain information. We employ a probabilistic model checking algorithm for verification, and demonstrate the applicability of this approach by a case study. Modeling and verification is achieved using the model checking tool PRISM. Based on the results, general specifications for modeling business processes using a probabilistic model checker are identified. Also, the difference between declarative and procedural business process modeling approaches is discussed. We propose to combine declarative and procedural techniques, thereby gaining increased expressiveness in modeling business processes, but still maintain verification feasible.

Deciding Reachability for 3-Dimensional Multi-Linear Systems

This paper deals with the problem of point-to-point reachability in multi-linear systems. These systems consist of a partition of the Euclidean space into a finit e number of regions and a constant derivative assigned to each region in the partition, which g overns the dynamical behavior of the system within it. The reachability problem for multi-linear sy stems has been proven to be decidable for the two-dimensional case and undecidable for the dimension three and higher. Multi-linear systems however exhibit certain properties that make them very suitable for topological analysis. We prove that reachability can be decided exactly in the 3-dimensional case when systems satisfy certain conditions. We show with experiments that our approach can be orders of magnitude more efficient than simulation.

A BDD-Representation for the logic of equality and uninterpreted functions

The logic of equality and uninterpreted functions (EUF) has been proposed for processor verification. This paper presents a new data structure called Binary Decision Diagrams for representing EUF formulas (EUF-BDDs). We define EUF-BDDs similar to BDDs, but we allow equalities between terms as labels instead of Boolean variables. We provide an approach to build a reduced ordered EUF-BDD (EUF-ROBDD) and prove that every path to a leaf is satisfiable by construction. Moreover, EUF-ROBDDs are logically equivalent representations of EUF-formulae, so they can also be used to represent state spaces in symbolic model checking with data.

Comparing techniques for proving unsatisfiability

We compare two standard techniques for satisfiability (SAT), which are basic for verification of microprocessor systems. We propose an approach for construction of shorter resolution refutations based on a standard approach called DPLL.