Oliver Krammer

Comparing the reliability and intermetallic layer of solder joints prepared with infrared and vapour phase soldering

Purpose – The purpose of this paper is to compare the reliability and intermetallic layer (IML) of solder joints prepared with infrared (IR) and vapour phase (VP) soldering. The reliability of 0603-sized resistors’ solder joints formed with IR and VP soldering was investigated. The IML of the joints was analysed based on image processing algorithm automatically. Design/methodology/approach – For the reliability analyses, the ageing method was a highly accelerated stress test (HAST) with +105°C maximum temperature, fully saturated (100 per cent) relative humidity at +0.5 atm overpressure. The joints were characterised based on the thickness of their IML and on their shear strength in as-reflowed stage, and after 400, 800, 1,200, 1,600 and 2,000 hours of HAST. An image processing algorithm was developed to measure the thickness of the IMLs on cross-sectional scanning electron microscopy (SEM) images automatically. Findings – The increase of the IML thickness is lower in the case of HAST ageing compared to o...

Investigating the mechanical strength of Vapor Phase soldered chip components joints

In our experiment the mechanical strength of solder joints formed by Vapor Phase soldering was investigated. A testboard was designed, which allowed fifty pieces of 0603 size chip resistors to be placed. The soldering was carried out by infrared conventional reflow and by Vapor Phase reflow as well. After soldering the shear strength of joints formed by both of the soldering methods was measured, and the cross-section of solder joints was analyzed by Scanning Electron Microscopy. Based on the results, it can be said that the shear strength of joints formed by Vapor Phase soldering is slightly lower than the strength of joints formed by IR reflow. The thermal profile of Vapor Phase soldering needs further optimization. The detailed results are presented in the paper.

Solder Paste Scooping Detection by Multilevel Visual Inspection of Printed Circuit Boards

In this paper, we introduce an automated Bayesian visual inspection framework for printed circuit board (PCB) assemblies, which is able to simultaneously deal with various shaped circuit elements (CEs) on multiple scales. We propose a novel hierarchical multi-marked point process model for this purpose and demonstrate its efficiency on the task of solder paste scooping detection and scoop area estimation, which are important factors regarding the strength of the joints. A global optimization process attempts to find the optimal configuration of circuit entities, considering the observed image data, prior knowledge, and interactions between the neighboring CEs. The computational requirements are kept tractable by a data-driven stochastic entity generation scheme. The proposed method is evaluated on real PCB data sets containing 125 images with more than 10 000 splice entities.

Comparing the intermetallic layer formation of Infrared and Vapour Phase soldering

In our experiment the intermetallic layer (IML) formation during Infrared (IR) and Vapour Phase (VP) soldering was investigated. A testboard was designed, onto which fifty pieces of 0603 (1.5 × 0.75 mm) size chip resistors were mounted. For the soldering, profiles with different Qη factors (750, 1000, 1250 s°C) were set for both the IR and VP soldering. After soldering, the shear strength and the intermetallic layer (IML) thickness were measured of joints formed by both of the soldering methods. The shear strength was measured according to industrial standards; the shearing speed was 100 µm/s. Afterwards, solder joints were cross-sectioned for the IML thickness measurements. The cross-section of the solder joints was inspected by Scanning Electron Microscopy and the IML thickness was measured by analyzing the SEM images. The image analysis method is based on image binarization and the code is developed in Matlab. The threshold level for the image binarization is determined by the mean value of a Gauss curve fitted onto the histogram of the SEM image. The image analysis method and the detailed results are presented in the paper.

Board level investigation of BGA solder joint deformation strength

Abstract In this paper we present a method to determine the stress in BGA solder joints on complex, real assembled circuit boards. To be able to investigate the mechanical effects of post-reflow assembly within the solder joints of BGA components, it is necessary to undertake a mechanical investigation at board level by taking into consideration the effect of the adjacent components and the interconnection layer layouts. In our project, we have developed a method of how to investigate the board level deformation strength of BGA joints. The elastic properties of a real assembled circuit board and of a circuit bare board are measured; an FEM model is then created, both of the bare board and of the assembled printed circuit board taking into account the layout of the interconnection layers. The advantage of this PCB FEM model is that the deformation of a PCB of any size and for any load can be calculated quickly using any ordinary computer. In our project, we also have created another detailed FEM model for the BGA solder joints. Using the constructed FEM models, we are able to determine the stress in BGA solder joints on a real electronic product for a typical type of load (i.e. bending of PCB) thereby verifying our method. Since the simulated results correspond well to previous literature written on this topic, we consider that our method is appropriate for calculating stress in the solder joints of multi-lead components on complex, fully assembled circuit boards.

Improved method for determining the shear strength of chip component solder joints

Abstract In this paper an improved method has been presented to determine the solder joint shear strength of passive discrete surface mounted (SMD) chip components (like resistors and capacitors). To calculate the stress in a solder joint in the case of shear loading, the force applied should be measured and the amount of joined surface (wetted area of the component metallization) calculated. Using the method we suggest, we first measured the exact position of the chip component after soldering according to the guidelines set out in standard IPC 9850 (Institute for Interconnecting and Packaging Electronic Circuits). To determine the accurate value of the joined surface, a 3D profile calculation was carried out taking into account the exact position of chip components after soldering. The calculation of the profile was based on the principle of minimum energy. Then, the next stage was to determine the maximum force experimentally that the solder joint was able to withstand before failure in shear. The evaluation of the shear load results verified that the standard deviation coefficient of the results was lower when the shear strength of the solder is characterized by the maximum stress instead of maximum force. It was proved by our experiments and by simulations that the shear strength of misaligned components solder joints depends on the degree of component misalignment after reflow soldering.

Lead-Free Soldering Technology Review - Evaluating Solder Pastes and Stencils

Lead-free solders differ from lead-bearing solders in several properties such as surface tension, wetting ability, etc. In paste form they have greater adhesion force, so they can block small stencil apertures more easily. Because of this fact, the printing parameters and stencils design criterias have to be changed. Since lead-free soldering has to be implemented in the electronic industry until 1st of July 2006, selection of the appropriate pastes and stencils is more important than ever. In our experiment six TSC (Tin-Silver-Copper) solders from different suppliers were evaluated from aspects of wetting properties, solderability and printability alike. Component self alignment was also investigated. In addition three kinds of stencils (lasercut stainless steel, lasercut nickel and electroformed nickel) were investigated as well by measuring transfer efficiency in function of area ratio of stencil-apertures. Results have shown that electroform stencils have outstanding printing properties while lasercut stencils (stainless steel and nickel) have similar capabilities independently of the material, thus it is not sure it is worth using lasercut nickel stencils for double the price. The evaluation of solders has revealed that the new lead-free pastes have equally excellent printing and soldering properties. Lead-free soldering with these pastes will not be problem.

Method for selective solder paste application for BGA rework

The reflow soldering of BGA (ball grid array) packaged components always raise quality and reliability issues since bridges and open joints can form easily due to the warpage of PCBs and packages. Since the highly integrated circuit boards are relatively expensive the rework of failed BGA packages is absolutely necessary. During the rework process the deposition of solder paste is one of the key issues, which is usually carried out by mini stencil printing and always gives a challenge for engineers in the case of large size fine pitch BGA packages. A solution can be to apply the solder paste by dipping the BGA package into the paste in the same way as in package on package (PoP) technology. Experiment and testboard was designed in order to investigate the quality of reworked BGA solder joints, which meant to be dipped into a newly developed low viscosity solder paste. In the experiment we plan to rework BGA packaged components in two ways; on one hand solder paste is deposited by stencil printing and on the other hand the packages are dipped into the newly developed paste. The solder joints are planned to be inspected by X-ray microscopy.

Testing the Impact of Pb-free Soldering on Reliability

The electronics industry is in the transition to lead-free technology, and it is very important for all industrial performers, to keep pace with this process. In order to produce the electronics module of required quality and reliability, the application of lead-free soldering alloys requires new design, materials, processing, inspection and rework considerations. It is also a new challenge to test and predict the reliability and the life-time of the lead-free solder joints fabricated with new materials combinations and process parameters. In the paper, the general requirements of solder joints, the theoretical considerations of the applicability of combined accelerated life-time test methods and the results of some experimental work regarding lead-free solder joints are discussed

New method for determining correction factors for pin-in-paste solder volumes

Purpose This paper aims to present a new method to calculate the appropriate volume of solder paste necessary for the pin-in-paste (PIP) technology. By the aid of this volume calculation, correction factors have been determined, which can be used to correct the solder fillet volume obtained by an explicit expression. Design/methodology/approach The method is based on calculating the optimal solder fillet shape and profile for through-hole (TH) components with given geometrical sizes. To calculate this optimal shape of the fillet, a script was written in Surface Evolver. The volume calculations were performed for different fillet radiuses (0.4-1.2 mm) and for different component lead geometries (circular and square cross-sections). Finally, the volume obtained by the Evolver calculations was divided by the volume obtained by an explicit expression, and correction factors were determined for the varying parameters. Findings The results showed that the explicit expression underestimates the fillet volume necessary for the PIP technology significantly (15-35 per cent). The correction factors for components with circular leads ranged between 1.4 and 1.59, whereas the correction factors for square leads ranged between 1.1 and 1.27. Applying this correction can aid in depositing the appropriate solder paste volume for TH components. Originality/value Determining the correct volume of solder paste necessary for the PIP technology is crucial to eliminate the common soldering failure of TH components (e.g. voiding or non-wetted solder pads). The explicit expression, which is widely used for volume calculation in this field, underestimates the necessary volume significantly. The new method can correct this estimation, and can aid the industry to approach zero-defect manufacturing in the PIP technology.