Oliver Pohland

Influence of junction capacitance on SRAM SEU performance [MOSFETs]

Source and drain junction capacitance has been varied by utilizing different implant conditions for the MOSFETs to explore the possibility of improving SEU (single event upset) immunity of SRAM cells. It is found. that the junction capacitances of both the n/sup +//p-well and p/sup +//n-well can vary in a wide range. The resulting SEU FIT (failure in time) rate shows a significant reduction. HSPICE simulation indicates that critical charge of the SRAM cell increases by 5%. The reduction of funnel length due to the higher doping concentration in the source/drain area also improves SEU immunity.

New Type of Dummy Layout Pattern to Control ILD etch Rate

Adding dummy features (waffles) to drawn geometries of the circuit layout is a common practice to improve its manufacturability. As an example, local dummy pattern improves MOSFET line and space CD control by adjusting short range optical proximity and reducing the aggressiveness of its correction features (OPC) to widen the lithography process window. Another application of dummy pattern (waffles) is to globally equalize layout pattern density, to reduce long-range inter-layer dielectric (ILD) thickness variations after the CMP process and improve contact resistance uniformity over the die area. In this work, we discuss a novel type of dummy pattern with a mid-range interaction distance, to control the ILD composition driven by its deposition and etch process. This composition is reflected on sidewall spacers and depends on the topography of the underlying poly pattern. During contact etch, it impacts the etch rate of the ILD. As a result, the deposited W filling the damascene etched self-aligned trench contacts in the ILD may electrically short to the underlying gates in the areas of isolated poly. To mitigate the dependence of the ILD composition on poly pattern distribution, we proposed a special dummy feature generation with the interaction range defined by the ILD deposition and etch process. This helped equalize mid-range poly pattern density without disabling the routing capability with damascene trench contacts in the periphery which would have increased the layout footprint.

A Low-Cost Strained Silicon SRAM Technology with Reduced Contact Resistance

This paper presents a simple and cost-effective method to enhance 65nm SRAM technology performance using a single stress liner, resulting in 25% increase in cell read current. A novel slot contact process allows significant improvement of NMOS drive current without PMOS degradation, by relaxing the undesirable strain in the PMOS. This new slot process also results in significant reduction of the S/D contact resistance.

Leakage increase of narrow and short BCPMOS

The leakage performance of BCPMOS (buried channel PMOS) is investigated by experimentally varying the LDD implant conditions. An anomalous leakage increase with a boron LDD implant is observed for a small geometry (narrow and short) PMOS. Experimental results indicate that the increase of leakage current for narrow and short channel PMOS can be explained by boron piling up at the edge of the STI and from the source/drain towards the middle of the channel. Further confirmation of boron piling up is proven by the surface channel NMOS threshold voltage. Based on the leakage sensitivity, the BC PMOS LDD is optimized to reduce the leakage current for small geometry transistors.

Optimization of interconnection layout for multitransistor cell shrinkability

The footprint of multi-transistor memory cell is limited by a complex connectivity layout. Depending on the architecture, the interconnect layers might be a hindrance in scaling the cell. This limitation is a result of the need for having multiple contacts to active or gate regions within small cell area as well as by the tight overlay requirements between these contacts and the overlaying metal. Minimum chrome line (i.e., contact space) CD of an attenuated phase shift mask used for printing these contacts as well as the mask and stepper alignment tolerances scale down slower than required by the technology roadmap. Moreover, the novel memory cell applications call for the increased cell complexity. In this work, we discuss how a combination of a new single damascene and self-aligned dual-damascene processes impact the area of a 6-Transistor Double-Wordline SRAM cell. We first identified the optimal cell architecture, followed by developing a unique interconnect scheme. In consequence, the area of the cell was reduced by as much as 25% within the 90 nm technology node. The new interconnect layer has been enabled at the expense of one additional mask.