Oliver Rose

Grand challenges in modeling and simulation of complex manufacturing systems

Even though we have moved beyond the Industrial Age and into the Information Age, manufacturing remains an important part of the global economy. There is a need for the pervasive use of modeling and simulation for decision support in current and future manufacturing systems, and several challenges need to be addressed by the simulation community to realize this vision. First, an order of magnitude reduction in problem-solving cycles is needed. The second grand challenge is the development of real-time, simulation-based problem-solving capability. The third grand challenge is the need for true plug-and-play interoperability of simulations and supporting software. Finally, there is the biggest challenge facing modeling and simulation analysts today: that of convincing management to sponsor modeling and simulation projects instead of, or in addition to, more commonly used manufacturing system design and improvement methods such as lean manufacturing and six sigma.

A survey of problems, solution techniques, and future challenges in scheduling semiconductor manufacturing operations

In this paper, we discuss scheduling problems in semiconductor manufacturing. Starting from describing the manufacturing process, we identify typical scheduling problems found in semiconductor manufacturing systems. We describe batch scheduling problems, parallel machine scheduling problems, job shop scheduling problems, scheduling problems with auxiliary resources, multiple orders per job scheduling problems, and scheduling problems related to cluster tools. We also present important solution techniques that are used to solve these scheduling problems by means of specific examples, and report on known implementations. Finally, we summarize some of the challenges in scheduling semiconductor manufacturing operations.

WIP evolution of a semiconductor factory after a bottleneck workcenter breakdown

In semiconductor fabrication facilities, an increase in work in progress (WIP) can be observed even weeks after the failure of the bottleneck workcenter. We develop a simple fab model that facilitates the study of this phenomenon. The simplified factory consists of a detailed model of the bottleneck workcenter and a delay unit that represents the rest of the factory. After passing the delay unit, the lots are fed back to the bottleneck to model the cyclic flow of lots of real wafer fabs. We study the behavior of this model for numerous scenarios, and it turns out that by means of the model, the WIP increase phenomenon can successfully be reproduced. In addition, we provide first results on how to avoid the unwanted increase in inventory.

CONLOAD—a new lot release rule for semiconductor wafer fabs

We present CONLOAD (CONstant LOAD), a new lot release rule for wafer fabs. It was developed to overcome some performance problems of traditional lot release rules such as CONWIP or Workload Regulation during product mix changes. We show that CONLOAD outperforms CONWIP and Workload Regulation with respect to keeping the bottleneck utilization at a desired level and to provide a smooth evolution of the WIP.

Some issues of the critical ratio dispatch rule in semiconductor manufacturing

In this paper, we examine the cycle time and on-time delivery performance of a semiconductor wafer fabrication facility (wafer fab) under critical ratio (CR) dispatch regime. It turns out that determining appropriate due dates for this rule is a critical task. We provide a detailed analysis of the wafer fab behavior for a large range of due date values. From the results of the experiments we develop an heuristic for conservative due date estimates.

A Simulation Framework for the Performance Assessment of Shop-Floor Control Systems

The authors discuss the concept and design criteria for a framework that facilitates the performance assessment of shop-floor control systems. Their basic concept includes a simulation model that emulates the shop floor of a wafer fab, sends information to the control system, and receives information back from the control system. The shop-floor control system is realized as a separate module that interfaces to the simulator via a data layer that contains the current shop-floor status and the control information generated by the controller. The authors provide detailed information on how the simulation model and shop-floor control system communicate and how each system triggers events in the other system. They show how this framework supports the performance assessment of the shop-floor control system under consideration. They also present a prototype of the framework currently implemented in the course of the SRC/International Sematech FORCe project “Scheduling of Semiconductor Wafer Fabrication Facilities.”

The shortest processing time first (SPTF) dispatch rule and some variants in semiconductor manufacturing

Looking for appropriate dispatch rules for semiconductor fabrication facilities (wafer fabs), practitioners often intend to use the Shortest Processing Time First (SPTF) rule because it is said to reduce cycle times. In our study, we show, however, that this positive effect on cycle times can be achieved in single machine systems but not necessarily in complete wafer fabs. In addition, we discuss variants of the SPTF rule.

Improved simple simulation models for semiconductor wafer factories

Semiconductor wafer fabrication facilities (wafer fabs) are among the most complex production facilities. A large product variety, hundreds of processing steps per product, hundreds of machines of different types, and automated transport lead to a system complexity which is hard to understand and hard to handle. For educating planners and developing adequate material flow control mechanisms, simple models for this complex environment are required. Several years ago, we published some first approaches which were useful to explain the fab behavior after a serious bottleneck breakdown. With that simple model, however, it was only possible to predict the cycle time distribution of the lots for a few scenarios. In this paper, we present some model improvements which lead to a rather good cycle time prediction for a variety of load situations.

Why do simple wafer fab models fail in certain scenarios

Previous work has proved that simple simulation models are sufficient for analyzing the behavior of complex wafer fabs in certain scenarios. We give an example where the simple model fails to accurately predict cycle times and WIP levels of the complex model. To determine the reason for this behavior, we analyze the correlation properties of a MIMAC (Measurement and Improvement of Manufacturing Capacity) full fab model and the corresponding simple one. It turns out that the simple model is not capable of capturing the correlations in an adequate way because there is lot overtaking (passing) in the simple model while almost no overtaking can be found in the complex counterpart.

First steps towards a general SysML model for discrete processes in production systems

In many areas of science, like computer science or electrical engineering, modeling languages have been established, however, this is not the case in the field of discrete processes (Weilkiens 2006). There are two reasons which motivate such a development: 1. Modeling languages allow realizing projects by the principles of systems engineering. So one obtains clearness even for large projects and reduces the discrepancy between model and reality. 2. Modeling languages are a central part of automatic code generation. In this paper, we present our first steps in developing a simulation-tool-independent description of production systems and first ideas on how to convert such a general model into simulation-tool-specific models.